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參數(shù)資料
| 型號(hào)： | MR80C52EXXX-16SHXXX:R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 65/143頁 |
| 文件大?。?/td> | 4602K |
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28
XMEGA A3BU [DATASHEET]
8362F–AVR–02/2013
15.
Interrupts and Programmable Multilevel Interrupt Controller
15.1
Features
Short and predictable interrupt response time
Separate interrupt configuration and vector address for each interrupt
Programmable multilevel interrupt controller
Interrupt prioritizing according to level and vector address
Three selectable interrupt levels for all interrupts: low, medium and high
Selectable, round-robin priority scheme within low-level interrupts
Non-maskable interrupts for critical functions
Interrupt vectors optionally placed in the application section or the boot loader section
15.2
Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
15.3
Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the Atmel AVR XMEGA A3BU devices are shown in Table 15-1. Offset
addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU manual. For
peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 15-1. The program address is
the word address.
Table 15-1. Reset and interrupt vectors.
Program address
(base address)
Source
Interrupt description
0x000
RESET
0x002
OSCF_INT_vect
Crystal oscillator failure interrupt vector (NMI)
0x004
PORTC_INT_base
Port C interrupt base
0x008
PORTR_INT_base
Port R interrupt base
0x00C
DMA_INT_base
DMA controller interrupt base
0x014
RTC32_INT_base
32-bit Real Time Counter interrupt base
0x018
TWIC_INT_base
Two-Wire Interface on Port C interrupt base
0x01C
TCC0_INT_base
Timer/Counter 0 on Port C interrupt base
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