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參數(shù)資料
| 型號： | MR80C52EXXX-16SHXXX:R |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 74/143頁 |
| 文件大?。?/td> | 4602K |
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36
XMEGA A3BU [DATASHEET]
8362F–AVR–02/2013
18.
TC2 – Timer/Counter Type 2
18.1
Features
Eight eight-bit timer/counters
Four Low-byte timer/counter
Four High-byte timer/counter
Up to eight compare channels in each Timer/Counter 2
Four compare channels for the low-byte timer/counter
Four compare channels for the high-byte timer/counter
Waveform generation
Single slope pulse width modulation
Timer underflow interrupts/events
One compare match interrupt/event per compare channel for the low-byte timer/counter
Can be used with the event system for count control
Can be used to trigger DMA transactions
18.2
Overview
There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of
two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width modulation
(PWM) channels with individually controlled duty cycles, and is intended for applications that require a high number of
PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare
match interrupts, events and DMA triggers. The two eight-bit timer/counters have a shared clock source and separate
period and compare settings. They can be clocked and timed from the peripheral clock, with optional prescaling, or from
the event system. The counters are always counting down.
PORTC, PORTD, PORTE and PORTF each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2),
TCD2, TCE2 and TCF2, respectively.
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相關(guān)代理商/技術(shù)參數(shù) |
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