參數(shù)資料
型號(hào)： MR80C52TXXX-16/883:RD
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
封裝： LCC-44
文件頁數(shù)： 57/109頁
文件大?。?/td> 10824K
37
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
A typical and general setup for interrupt vector addresses in ATtiny20 is shown in the program example below.
Note:
9.2
External Interrupts
External Interrupts are triggered by the INT0 pin or any of the PCINT[11:0] pins. Observe that, if enabled, the interrupts
will trigger even if the INT0 or PCINT[11:0] pins are configured as outputs. This feature provides a way of generating a
software interrupt.
Pin change 0 interrupts PCI0 will trigger if any enabled PCINT[7:0] pin toggles. Pin change 1 interrupts PCI1 will trigger if
any enabled PCINT[11:8] pin toggles. The PCMSK0 and PCMSK1 Registers control which pins contribute to the pin
change interrupts. Pin change interrupts on PCINT[11:0] are detected asynchronously, which means that these interrupts
can be used for waking the part also from sleep modes other than Idle mode.
The INT0 interrupt can be triggered by a falling or rising edge or a low level. This is set up as shown in “MCUCR – MCU
Control Register” on page 38. When the INT0 interrupt is enabled and configured as level triggered, the interrupt will
trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT0 requires the
presence of an I/O clock, as described in “Clock System” on page 17.
9.2.1
Low Level Interrupt
A low level interrupt on INT0 is detected asynchronously. This means that the interrupt source can be used for waking
the part also from sleep modes other than Idle (the I/O clock is halted in all sleep modes except Idle).
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level must be held long enough
for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up
Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined as described in “Clock
Assembly Code Example
.org 0x0000
;Set address of next
statement
rjmp
RESET
; Address 0x0000
rjmp
INT0_ISR
; Address 0x0001
rjmp
PCINT0_ISR
; Address 0x0002
rjmp
PCINT1_ISR
; Address 0x0003
rjmp
WDT_ISR
; Address 0x0004
rjmp
TIM1_CAPT_ISR
; Address 0x0005
rjmp
TIM1_COMPA_ISR
; Address 0x0006
rjmp
TIM1_COMPB_ISR
; Address 0x0007
rjmp
TIM1_OVF_ISR
; Address 0x0008
rjmp
TIM0_COMPA_ISR
; Address 0x0009
rjmp
TIM0_COMPB_ISR
; Address 0x000A
rjmp
TIM0_OVF_ISR
; Address 0x000B
rjmp
ANA_COMP_ISR
; Address 0x000C
rjmp
ADC_ISR
; Address 0x000D
rjmp
TWI_SLAVE_ISR
; Address 0x000E
rjmp
SPI_ISR
; Address 0x000F
rjmp
QTRIP_ISR
; Address 0x0010
RESET:
; Main program start
<instr>
; Address 0x0011
...
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