參數(shù)資料
型號: MR80C52TXXX-16/883:RD
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CQCC44
封裝: LCC-44
文件頁數(shù): 92/109頁
文件大?。?/td> 10824K
69
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
Figure 11-10.Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f
clk_I/O/8)
Figure 11-11 on page 69 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM mode
where OCR0A is TOP.
Figure 11-11.Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f
clk_I/O/8)
11.9
Register Description
11.9.1 TCCR0A – Timer/Counter Control Register A
Bits 7:6 – COM0A[1:0] : Compare Match Output A Mode
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A[1:0] bits are set, the OC0A
output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction
Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)
Bit
7
6
5
4
3
2
1
0
COM0A1
COM0A0
COM0B1
COM0B0
WGM01
WGM00
TCCR0A
Read/Write
R/W
R
R/W
Initial Value
0
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