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參數(shù)資料
| 型號(hào)： | MS622424 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | HIGH PERFORMANCE 8K x 24 BIT CMOS COLOR MAP |
| 中文描述： | 高性能8K的× 24位CMOS彩色地圖 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大小： | 70K |
| 代理商： | MS622424 |
8-7
MS622424
MOSEL V ITELIC
MS622424 Rev. 1.0 January 1995
Pin Descriptions
(Cont’d)
Pin Name
Description
RSB
Reset input pin. This asynchronous system reset initializes state machines and
resets the Address, Status, and Color Buffer registers. It also resets the Write
FIFO so that it is empty of any contents. It resets command register bits CB2–CB7
and sets bits CB0–CB1. During a reset, CONFIGBUS0–CONFIGBUS7 are in
tri-state. This pin is active low.
AFB
The FIFO status output pin. This active low output indicates that the Write FIFO is
half or almost full. This active low output can be programmed by a bit in the
Command Register to indicate that the FIFO is at least half full or is almost full
(eight or less empty locations left).
FFB
The FIFO status output pin. This active low output indicates that the Write FIFO
is full.
V
SS
/TEST
This pin should be grounded for normal operation.
BD.REV(0-3)
Board revision input pins. These input pins can be pull-up to V
DD
or pull-down to
V
SS
. The BD.REV data can be read though the revision register.
INPUT
POUT(0-23)
PIX.IN(0-23)
PIPE.IN(0-3)
ADDRESS
DECODER
SENSE
AMPLIFIER
OUTPUT
CLOCK.IN
PIPE.OUT(0-3)
LATCH 1
LATCH 4
LATCH 2
LATCH 3
24
4
Internal Pipeline Data Path for Pixel and Pipe Input Data
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