參數(shù)資料
型號： MSC8101VT1250F
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù)： 26/104頁
文件大?。?/td> 1811K
代理商： MSC8101VT1250F
MSC8101 Technical Data, Rev. 18
1-24
Freescale Semiconductor
Signals/Connections
1.6.3
Port C Signals
PB18
FCC2: RXD3
MII and HDLC nibble
I2C: SCL
Input
Input/Output
FCC2: MII and HDLC Nibble Receive Data Bit 3
RXD3 is bit 3 and the most significant bit of the receive data nibble.
I2C: Inter-Integrated Circuit Serial Clock
The I2C interface comprises two signals: serial data (SDA) and serial
clock (SDA). The I2C controller uses a synchronous, multimaster bus
that can connect several integrated circuits on a board. Clock rates run
up to 520 kHz@25 MHz system clock.
Table 1-9.
Port C Signals
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
PC31
BRG1O
CLK1
TIMER1/2: TGATE1
Output
Input
Baud-Rate Generator 1 Output
The CPM supports up to 8 BRGs used internally by the bank-of-clocks
selection logic and/or to provide an output to one of the 8 BRG pins.
BRG1O can be the internal input to the SIU timers. When CLK5 is selected
(see PC27 below), it is the source for BRG1O which is the default input for
the SIU timers. See the system interface unit (SIU) chapter in the
MSC8101 Reference Manual for additional information. If CLK5 is not
enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26
below), the BRG1O input to the SIU timers is disabled.
Clock 1
The CPM supports up to 10 clock input pins sent to the bank-of-clocks
selection logic, where they can be routed to the controllers.
Timer 1/2: Timer Gate 1
The timers can be gated/restarted by an external gate signal. There are
two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls
timer 3 and/or 4.
Table 1-8.
Port B Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
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