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參數(shù)資料
| 型號(hào)： | MSC8101VT1250F |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 64-BIT, 62.5 MHz, OTHER DSP, PBGA332 |
| 封裝： | 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332 |
| 文件頁數(shù)： | 31/104頁 |
| 文件大?。?/td> | 1811K |
| 代理商： | MSC8101VT1250F |
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MSC8101 Technical Data, Rev. 18
1-28
Freescale Semiconductor
Signals/Connections
PC24
BRG8O
CLK8
TIN3
Timer4: TOUT4
DMA: DREQ2
Output
Input
Output
Input
Baud-Rate Generator 8 Output
The CPM supports up to 8 BRGs used internally by the bank-of-clocks
selection logic and/or to provide an output to one of the 8 BRG pins.
Clock 8
The CPM supports up to 10 clock input pins. The clocks are sent to the
bank-of-clocks selection logic, where they can be routed to the controllers.
Timer Input 3
A timer can have one of the following sources: another timer, system
clock, system clock divided by 16, or a timer input. The CPM supports up
to four timer inputs. The timer inputs can be captured on the rising, falling,
or both edges.
Timer 4: Timer Out 4
The timers (Timer1–4]) can output a signal on a timer output (TOUT[1–4])
when the reference value is reached. This signal can be an active-low
pulse or a toggle of the current output. The output can also be connected
internally to the input of another timer, resulting in a 32-bit timer.
DMA: Data Request 2
DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA controller.
DONE2 and DRACK2 are signals on the same pin and therefore cannot be
used simultaneously. There are two sets of DMA pins associated with the
PIO ports.
PC23
CLK9
DMA: DACK1
EXT2
Input
Output
Input
Clock 9
The CPM supports up to 10 clock input pins sent to the bank-of-clocks
selection logic, where they can be routed to the controllers.
DMA: Data Acknowledge 1
DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller.
DONE1 and DRACK1 are signals on the same pin and therefore cannot be
used simultaneously. There are two sets of DMA pins associated with the
PIO ports.
External Request 2
External request input line 2 asserts an internal request to the CPM
processor. The signal can be programmed as level- or edge-sensitive, and
also has programmable priority. Refer to the risc controller configuration
register (RCCR) description in the Chapter 17 of the
MSC8101 Reference
Manual for programming information. There are no current microcode
applications for this request line. It is reserved for future development.
Table 1-9.
Port C Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
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