參數(shù)資料
型號： MSC8101VT1250F
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù)： 94/104頁
文件大?。?/td> 1811K
代理商： MSC8101VT1250F
Reset, Configuration, and EOnCE Event Signals
MSC8101 Technical Data, Rev. 18
Freescale Semiconductor
1-5
1.3 Reset, Configuration, and EOnCE Event Signals
CLKOUT
Output
Clock Out
The system bus clock.
DLLIN
Input
DLLIN
Synchronizes with an external device.
Note:
When the DLL is disabled, connect this signal to GND.
Table 1-4.
Reset, Configuration, and EOnCE Event Signals
Signal Name
Type
Signal Description
DBREQ
EE01
Input
Output
Debug Request
Determines whether to go into SC140 Debug mode when PORESET is deasserted.
Enhanced OnCE (EOnCE) Event 0
After PORESET is deasserted, you can configure EE0 as an input (default) or an output.
Debug request, enable Address Event Detection Channel 0, or generate an EOnCE event.
Detection by Address Event Detection Channel 0. Used to trigger external debugging equipment.
HPE
EE11
Input
Output
Host Port Enable
When this pin is asserted during PORESET, the Host port is enabled, the system data bus is 32 bits
wide, and the Host
must program the reset configuration word.
EOnCE Event 1
After PORESET is deasserted, you can configure EE1 as an input (default) or an output.
Enable Address Event Detection Channel 1 or generate an EOnCE event.
Debug Acknowledge or detection by Address Event Detection Channel 1. Used to trigger external
debugging equipment.
EE21
Input
Output
EOnCE Event 2
After PORESET is deasserted, you can configure EE2 as an input (default) or an output.
Enable Address Event Detection Channel 2 or generate an EOnCE event or enable the Event
Counter.
Detection by Address Event Detection Channel 2. Used to trigger external debugging equipment.
EE31
Input
Output
EOnCE Event 3
After PORESET is deasserted, you can configure EE3 as an input (default) or an output. See the
emulation and debug chapter in the
SC140 DSP Core Reference Manual for details on the ERCV
Register.
Enable Address Event Detection Channel 3 or generate one of the EOnCE events.
The DSP has read the EOnCE Receive Register (ERCV). Triggers external debugging equipment.
Table 1-3.
Clock Signals (Continued)
Signal Name
Type
Signal Description
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