參數(shù)資料
型號： MSC8101VT1250F
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 64-BIT, 62.5 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù)： 59/104頁
文件大?。?/td> 1811K
代理商： MSC8101VT1250F
MSC8101 Technical Data, Rev. 18
2-18
Freescale Semiconductor
Physical and Electrical Specifications
2.6.6
HDI16 Signals
Table 2-19.
Host Interface (HDI16) Timing1, 2
Number
Characteristics3
Expression
Value
Unit
44a
Read data strobe minimum assertion width4
HACK read minimum assertion width
(1.5
× TC) + 5.0
Note 11
ns
44b
Read data strobe minimum deassertion width4
HACK read minimum deassertion width
TC + 5.0
Note 11
ns
44c
Read data strobe minimum deassertion width4 after “Last Data Register”
reads5,6, or between two consecutive CVR, ICR, or ISR reads7
HACK minimum deassertion width after “Last Data Register” reads5,6
(2.5
× TC) + 5.0
Note 11
ns
45
Write data strobe minimum assertion width8
HACK write minimum assertion width
(1.5
× TC) + 5.0
Note 11
ns
46
Write data strobe minimum deassertion width8
HACK write minimum deassertion width after ICR, CVR and Data Register
writes5
(2.5
× TC) + 5.0
Note 11
ns
47
Host data input minimum set-up time before write data strobe deassertion8
Host data input minimum set-up time before HACK write deassertion
—
5.0
ns
48
Host data input minimum hold time after write data strobe deassertion8
Host data input minimum hold time after HACK write deassertion
—
5.0
ns
49
Read data strobe minimum assertion to output data active from high
impedance4
HACK read minimum assertion to output data active from high impedance
—
5.0
ns
50
Read data strobe maximum assertion to output data valid4
HACK read maximum assertion to output data valid
(2.0
× TC) + 5.0
Note 11
ns
51
Read data strobe maximum deassertion to output data high impedance4
HACK read maximum deassertion to output data high impedance
—
5.0
ns
52
Output data minimum hold time after read data strobe deassertion4
Output data minimum hold time after HACK read deassertion
—
5.0
ns
53
HCS[1–2] minimum assertion to read data strobe assertion4
—5.0
ns
54
HCS[1–2] minimum assertion to write data strobe assertion8
—5.0
ns
55
HCS[1–2] maximum assertion to output data valid
TC + 5.0
Note 11
ns
56
HCS[1–2] minimum hold time after data strobe deassertion9
—0.0
ns
57
HA[0–3], HRW minimum set-up time before data strobe assertion9
Read
Write
—
0
5.0
ns
58
HA[0–3], HRW minimum hold time after data strobe deassertion9
—5.0
ns
61
Maximum delay from read data strobe deassertion to host request deassertion
for “Last Data Register” read4, 5, 10
(3.5
× TC) + 5.0
Note 11
ns
62
Maximum delay from write data strobe deassertion to host request deassertion
for “Last Data Register” write5,8,10
(3.0
× TC) + 5
Note 11
ns
63
Minimum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1)
deassertion to HREQ assertion.
(5.0
× TC) + 5.0
Note 11
ns
64
Maximum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1)
assertion to HREQ deassertion
(3.5
× TC) + 5.0
Note 11
ns
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