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參數(shù)資料
| 型號： | MSC8101VT1500F |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 64-BIT, 75 MHz, OTHER DSP, PBGA332 |
| 封裝： | 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332 |
| 文件頁數(shù)： | 30/104頁 |
| 文件大小： | 1811K |
| 代理商： | MSC8101VT1500F |
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CPM Ports
MSC8101 Technical Data, Rev. 18
Freescale Semiconductor
1-27
PC26
BRG6O
CLK6
Timer3: TOUT3
TMCLK
Output
Input
Output
Input
Baud-Rate Generator 6 Output
The CPM supports up to 8 BRGs used internally by the bank-of-clocks
selection logic and/or provide an output to one of the 8 BRG pins.
Clock 6
The CPM supports up to 10 clock input pins sent to the bank-of-clocks
selection logic, where they can be routed to the controllers.
Timer 3: Timer Out 3
The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4])
when the reference value is reached. This signal can be an active-low
pulse or a toggle of the current output. The output can also connect
internally to the input of another timer, resulting in a 32-bit timer.
Timer Clock
When selected, TMCLK is the designated input to the SIU timers. When
TMCLK is configured as the input to the SIU timers, the BRG1O input is
disabled. See the
System Interface Unit (SIU) chapter in the MSC8101
Reference Manual for additional information.
PC25
BRG7O
CLK7
TIN4
DMA: DACK2
Output
Input
Output
Baud-Rate Generator 7 Output
The CPM supports up to 8 BRGs used internally by the bank-of-clocks
selection logic and/or provide an output to one of the 8 BRG pins.
Clock 7
The CPM supports up to 10 clock input pins sent to the bank-of-clocks
selection logic, where they can be routed to the controllers.
Timer Input 4
A timer can have one of the following sources: another timer, system
clock, system clock divided by 16 or a timer input. The CPM supports up to
4 timer inputs. The timer inputs can be captured on the rising, falling or
both edges.
DMA: Data Acknowledge 2
DACK2, DREQ2, DRACK2 and DONE2 belong to the SIU DMA controller.
DONE2 and DRACK2 are signals on the same pin and therefore cannot be
used simultaneously. There are two sets of DMA pins associated with the
PIO ports.
Table 1-9.
Port C Signals (Continued)
Name
Dedicated
I/O Data
Direction
Description
General-
Purpose I/O
Peripheral Controller:
Dedicated I/O
Protocol
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