參數資料
型號： MSC8101VT1500F
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數字信號處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數： 51/104頁
文件大?。?/td> 1811K
代理商： MSC8101VT1500F
MSC8101 Technical Data, Rev. 18
2-10
Freescale Semiconductor
Physical and Electrical Specifications
2.6.4.2 Power-On Reset Flow
Asserting the PORESET external pin initiates the power-on reset flow.
Note:
PORESET
and TRST must be asserted externally for the duration of the power-up sequence.
As Table 2-13 shows, the MSC8101 has five configuration pins, four of which are multiplexed with the SC140
EONCE Event (EE[0–1], EE[4–5]) pins and the fifth of which is the RSTCONF pin. These pins are sampled at the
rising edge of PORESET. In addition to these configuration pins, three (MODCK[1–3]) pins are sampled by the
MSC8101. The signals on these pins and the MODCK_H value in the Hard Reset Configuration Word determine
the PLL locking mode, by defining the ratio between the DSP clock, the bus clocks, and the CPM clock
frequencies.
Table 2-13.
External Configuration Signals
Pin
Description
Settings
RSTCONF
Reset Configuration
Input line sampled by the MSC8101 at the rising edge of
PORESET.
0
Reset Configuration Master.
1
Reset Configuration Slave.
DBREQ/ EE0
EONCE Event Bit 0
Input line sampled after SC140 core PLL locks. Holding EE0
high when PORESET is deasserted puts the SC140 into
Debug mode.
0
SC140 starts the normal processing
mode after reset.
1
SC140 enters Debug mode immediately
after reset.
HPE/EE1
Host Port Enable
Input line sampled at the rising edge of PORESET. If
asserted, the Host port is enabled, the system data bus is
32-bit wide, and the Host
must program the reset
configuration word.
0
Host port disabled (hardware reset
configuration enabled).
1
Host port enabled.
BTM[0–1]/
EE[4–5]
Boot Mode
Input lines sampled at the rising edge of PORESET, which
determine the MSC8101 Boot mode.
00
MSC8101 boots from external memory.
01
MSC8101 boots from HDI16.
10
Reserved.
11
Reserved.
Table 2-14.
Reset Timing
No.
Characteristics
Expression
Min
Max
Unit
1
Required external PORESET duration minimum
CLKIN = 18 MHz
CLKIN = 75 MHz
16
/ CLKIN
888.8
213.3
—
ns
2
Delay from deassertion of external PORESET to deassertion of
internal PORESET
CLKIN = 18 MHz
CLKIN = 75 MHz
1024
/ CLKIN
56.89
13.65
s
3
Delay from deassertion of internal PORESET to SPLL lock
SPLLMFCLK = 18 MHz
SPLLMFCLK = 25 MHz
800
/ SPLLMFCLK
44.4
32.0
s
4
Delay from SPLL lock to DLL lock
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
DLL disabled
3073
/ BLCK
—
170.72
40.97
0.0
s
ns
5
Delay from SPLL lock to HRESET deassertion
DLL enabled
— BCLK = 18 MHz
— BCLK = 75 MHz
DLL disabled
— BCLK = 18 MHz
— BCLK = 75 MHz
3585
/ BLCK
512
/ BLCK
199.17
47.5
28.4
6.83
s
相關PDF資料
PDF描述
MSC8101M1375F 64-BIT, 68.75 MHz, OTHER DSP, PBGA332
MSC8126VT8000 0-BIT, 500 MHz, OTHER DSP, PBGA431
MSC8126TMP6400 0-BIT, 400 MHz, OTHER DSP, PBGA431
MSM5055 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, UUC94
MSM6051L 4-BIT, MROM, 0.032768 MHz, MICROCONTROLLER, UUC102
相關代理商/技術參數
參數描述
MSC8102 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
MSC81020 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS GENERAL PURPOSE AMPLIFIER APPLICATIONS
MSC8102M4000 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
MSC8102M4400 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
MSC8102RM 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Quad Core 16-Bit Digital Signal Processor
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數量 廠商 批號 封裝
添加更多采購

我的聯系方式

*
*
*