參數(shù)資料
型號: MSC8101VT1500F
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝: 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁數(shù): 66/104頁
文件大?。?/td> 1811K
代理商: MSC8101VT1500F
MSC8101 Technical Data, Rev. 18
2-24
Freescale Semiconductor
Physical and Electrical Specifications
Note:
The timing values refer to minimum system timing requirements. Actual implementation requires
conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and
output signals associated with the referenced internal controllers and supported communication protocols.
For example, FCC1 supports ATM/Utopia operation in slave mode, multi-PHY master direct polling
mode, and multi-PHY master multiplexed polling mode and each of these modes supports its own set of
signals; the direction (input or output) of some of the shared signal names depends on the selected mode.
2.6.8
JTAG Signals
Figure 2-22.
TDM Signal Diagram
Figure 2-23.
PIO, Timer, and DMA Signal Diagram
Table 2-22.
JTAG Timing
No.
Characteristics
All frequencies
Unit
Min
Max
500
TCK frequency of operation
0.0
40.0
MHz
501
TCK cycle time
25.0
ns
502
TCK clock pulse width measured at 1.6 V
12.5
ns
503
TCK rise and fall times
0.0
3.0
ns
508
TMS, TDI data set-up time
6.0
ns
509
TMS, TDI data hold time
3.0
ns
510
TCK low to TDO data valid
0.0
15.0
ns
511
TCK low to TDO high impedance
0.0
20.0
ns
512
TRST assert time
100.0
ns
513
TRST set-up time to TCK low
40.0
ns
Serial input clock
TDM inputs
TDM outputs
20
21
40
DLLIN
PIO/TIMER/DMA inputs
PIO/TIMER/DMA outputs
22
23
42
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