參數(shù)資料
型號(hào)： MSC8101VT1500F
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 64-BIT, 75 MHz, OTHER DSP, PBGA332
封裝： 17 X 17 MM, LIDDED FLIP CHIP, PLASTIC, BGA-332
文件頁(yè)數(shù)： 55/104頁(yè)
文件大?。?/td> 1811K
代理商： MSC8101VT1500F
MSC8101 Technical Data, Rev. 18
2-14
Freescale Semiconductor
Physical and Electrical Specifications
11g
TS set-up time before the 50% level of the DLLIN rising edge
5.0
ns
11h
BG set-up time before the 50% level of the DLLIN rising edge
4.5
ns
12
Data bus set-up time before the 50% level of the DLLIN rising edge in Normal
Pipeline mode
Non-pipeline mode
2.5
5.0
ns
13
Data bus set-up time before the 50% level of the DLLIN rising edge in ECC and PARITY modes
Pipeline mode
Non-pipeline mode
2.5
8.0
ns
14
DP set-up time before the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
4.0
9.0
ns
15a
Address bus set-up time before the 50% level of the DLLIN rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
Non-extra cycle mode (SIUBCR[EXDD] = 1)
5.0
8.0
ns
15b
Address attributes: TT/TBST/TSIZ/GBL set-up time before the 50% level of the DLLIN rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
Non-extra cycle mode (SIUBCR[EXDD] = 1)
5.0
5.5
ns
161
PUPMWAIT/IRQ signals set-up time before the 50% level of the DLLIN rising edge
3.0
ns
Notes:
1.
The set-up time for these signals is for synchronous operation. Any set-up time can be used for asynchronous operation.
2.
Input specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are
measured at the pin.
Table 2-17.
AC Timing for SIU Outputs
No.
Characteristic
Min.
Maximum2
Units
30 pF
50 pF
31a
TA delay from the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
1.0
5.0
4.0
6.5
5.5
ns
31b
TEA delay from the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
1.0
3.0
3.5
4.5
5.0
ns
31c
PSDVAL delay from the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
1.0
4.0
3.5
5.5
5.0
ns
32a
Address bus delay from the 50% level of the DLLIN rising edge
Multi master mode (SIUBCR[EBM] = 1)
Single master mode (SIUBCR[EBM] = 0)
1.0
6.3
5.5
7.8
7.0
ns
32b
Address attributes: TT/TBST/TSIZ/GBL delay from the 50% level of the DLLIN rising edge
1.0
5.5
7.0
ns
32c
BADDR delay from the 50% level of the DLLIN rising edge
1.0
3.5
5.0
ns
33a
Data bus delay from the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
1.0
5.0
6.0
6.5
7.5
ns
33b
DP delay from the 50% level of the DLLIN rising edge
Pipeline mode
Non-pipeline mode
1.0
4.0
6.5
5.5
8.0
ns
34
Memory controller signals/ALE delay from the 50% level of the DLLIN rising edge
1.0
5.5
7.0
ns
35a
DBG/BR/DBB delay from the 50% level of the DLLIN rising edge
1.0
4.0
5.5
ns
35b
AACK/ABB/CS delay from the 50% level of the DLLIN rising edge
1.0
4.5
6.0
ns
Table 2-16.
AC Timing for SIU Inputs
No.
Characteristic
Value2
Units
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