參數(shù)資料
型號: MSC8126TMP6400
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, 400 MHz, OTHER DSP, PBGA431
封裝: 20 X 20 MM, PLASTIC, FCBGA-431
文件頁數(shù): 19/48頁
文件大小: 1138K
代理商: MSC8126TMP6400
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Electrical Characteristics
Freescale Semiconductor
26
2.5.5.2
CLKIN to CLKOUT Skew
Table 17 describes the CLKOUT-to-CLKIN skew timing.
For designs that use the CLKOUT synchronization mode, use the skew values listed in Table 16 to adjust the rise-to-fall timing
values specified for CLKIN synchronization. Figure 12 shows the relationship between the CLKOUT and CLKIN timings.
Table 16. CLKOUT Skew
No.
Characteristic
Min1
Max1
Units
20
Rise-to-rise skew
00.85
ns
21
Fall-to-fall skew
–0.8
1.0
ns
22
CLKOUT phase high and low (1.2 V, 133 MHz)
2.8
ns
Notes:
1.
A positive number indicates that CLKOUT precedes CLKIN, A negative number indicates that CLKOUT follows CLKIN.
2.
Skews are measured in clock mode 29, with a CLKIN:CLKOUT ratio of 1:1. The same skew is valid for all clock modes.
3.
CLKOUT skews are measured using a load of 10 pF.
4.
CLKOUT skews and phase are not measured for 500/166 Mhz parts because these parts only use CLKIN mode.
Figure 12. CLKOUT and CLKIN Signals.
CLKIN
CLKOUT
20
21
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