參數資料
型號： MSC8126TMP6400
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數字信號處理
英文描述： 0-BIT, 400 MHz, OTHER DSP, PBGA431
封裝： 20 X 20 MM, PLASTIC, FCBGA-431
文件頁數： 8/48頁
文件大小： 1138K
代理商： MSC8126TMP6400
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Electrical Characteristics
Freescale Semiconductor
16
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When
systems such as DSP farms are developed using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 20 pF
load, except where noted otherwise, and a 50
Ω transmission line. For loads smaller than 20 pF, subtract 0.06 ns per pF down
to 10 pF load. For loads larger than 20 pF, add 0.06 ns for SIU/Ethernet/DSI delay and 0.07 ns for GPIO/TDM/timer delay.
When calculating overall loading, also consider additional RC delay.
2.5.1
Output Buffer Impedances
2.5.2
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3
describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the
following guidelines when starting up an MSC8126 device:
PORESET
and TRST must be asserted externally for the duration of the power-up sequence. See Table 11 for timing.
If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDD
levels and then the VDDH levels (see Figure 7).
CLKIN
should start toggling at least 16 cycles (starting after VDDH reaches its nominal level) before PORESET
deassertion to guarantee correct device operation (see Figure 6 and Figure 7).
CLKIN
must not be pulled high during VDDH power-up. CLKIN can toggle during this period.
Note:
See Section 3.1 for start-up sequencing recommendations and Section 3.2 for power supply design
recommendations.
The following figures show acceptable start-up sequence examples. Figure 6 shows a sequence in which VDD and VDDH are
raised together. Figure 7 shows a sequence in which VDDH is raised after VDD and CLKIN begins to toggle as VDDH rises.
Figure 5. Overshoot/Undershoot Voltage for VIH and VIL
Table 6. Output Buffer Impedances
Output Buffers
Typical Impedance (
Ω)
System bus
50
Memory controller
50
Parallel I/O
50
Note:
These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature.
GND
GND – 0.3 V
GND – 0.7 V
VIL
VIH
Must not exceed 10% of clock period
VDDH + 17%
VDDH + 8%
VDDH
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