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參數(shù)資料
| 型號： | MSC8126TMP6400 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, 400 MHz, OTHER DSP, PBGA431 |
| 封裝： | 20 X 20 MM, PLASTIC, FCBGA-431 |
| 文件頁數(shù)： | 36/48頁 |
| 文件大?。?/td> | 1138K |
| 代理商： | MSC8126TMP6400 |
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Hardware Design Considerations
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
41
Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 33 shows three
capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount
at least one of the capacitors directly below the MSC8126 device.
Each VCC and VDD pin on the MSC8126 device should have a low-impedance path to the board power supply. Similarly, each
GND
pin should have a low-impedance path to the ground plane. The power supply pins drive distinct groups of logic on the
chip. The VCC power supply should have at least four 0.1 F by-pass capacitors to ground located as closely as possible to the
four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should
be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and
GND
planes.
All output pins on the MSC8126 have fast rise and fall times. PCB trace interconnection length should be minimized to
minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to
the address and data buses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in
synchronous mode, ensure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk.
Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to
proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.
Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins:
VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to the one in
Figure 34. For optimal noise filtering, place the circuit as close as possible to VCCSYN. The 0.01-F capacitor should be closest
to VCCSYN, followed by the 10-F capacitor, the 10-nH inductor, and finally the 10-Ω resistor to VDD. These traces should be
kept short and direct. Provide an extremely low impedance path to the ground plane for GNDSYN. Bypass GNDSYN to VCCSYN
by a 0.01-F capacitor located as close as possible to the chip package. For best results, place this capacitor on the backside of
the PCB aligned with the depopulated void on the MSC8126 located in the square defined by positions, L11, L12, L13, M11,
M12, M13, N11, N12, and N13.
Figure 33. Core Power Supply Decoupling
Figure 34. VCCSYN Bypass
+
-
Power supply
or
Voltage Regulator
High frequency capacitors
(very low ESR and ESL)
Bulk/Tantalum capacitors
with low ESR and ESL
MSC8122
Maximum IR drop
of 15 mV at 1 A
Note: Use at least three capacitors.
Lmax = 2 cm
One 0.01 F capacitor
for every 3 core supply
(Imin = 3 A)
pads.
1.2 V
Each capacitor must be at least 150
μF.
VDD
0.01 F
10 F
VCCSYN
10
Ω
10nH
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