參數(shù)資料
型號(hào)： MSC8256SVT800B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783
文件頁(yè)數(shù)： 27/68頁(yè)
文件大?。?/td> 910K
代理商： MSC8256SVT800B
Electrical Characteristics
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
33
2.5.3.4
DC-Level Requirements for SGMII Configurations
Note:
Specifications are valid at the recommended operating conditions listed in Table 3
Table 15 describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics. Transmitter DC characteristics are
measured at the transmitter outputs (SR[1–2]_TX[n] and SR[1–2]_TX[n]) as shown in Figure 10.
Table 14. Serial RapidIO Receiver DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Notes
Differential input voltage
VIN
200
—
1600
mVp-p
1
Notes:
1.
Measured at receiver.
Table 15. SGMII DC Transmitter Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Output high voltage
VOH
——
XVDD_SRDS-Typ/2 + |VOD|-max/2
mV
1
Output low voltage
VOL
XVDD_SRDS-Typ/2 – |VOD|-max/2
—
mV
1
Output differential
voltage (XVDD-Typ at
1.0 V)
|VOD|
323
500
725
mV
2,3,4
296
459
665
2,3,5
269
417
604
2,3,6
243
376
545
2,3,7
215
333
483
2,3,8
189
292
424
2,3,9
162
250
362
2,3,10
Output impedance
(single-ended)
RO
40
50
60
Ω
—
Notes:
1.
This does not align to DC-coupled SGMII. XVDD_SRDS2-Typ = 1.1 V.
2.
The |VOD| value shown in the table assumes full multitude by setting srd_smit_lvl as 000 and the following transmit
equalization setting in the XMITEQAB (for lanes A and B) or XMITEQEF (for lanes E and F) bit field of Control Register:
The MSB (bit 0) of the above bit field is set to zero (selecting the full VDD-DIFF-p-p amplitude which is power up default);
The LSB (bit [1–3]) of the above bit field is set based on the equalization settings listed in notes 4 through 10.
3.
The |VOD| value shown in the Typ column is based on the condition of XVDD_SRDS2-Typ = 1.0 V, no common mode offset
variation (VOS =500mV), SerDes transmitter is terminated with 100-Ω differential load between
4.
Equalization setting: 1.0x: 0000.
5.
Equalization setting: 1.09x: 1000.
6.
Equalization setting: 1.2x: 0100.
7.
Equalization setting: 1.33x: 1100.
8.
Equalization setting: 1.5x: 0010.
9.
Equalization setting: 1.71x: 1010.
10. Equalization setting: 2.0x: 0110.
11. |VOD| = |VSR[1–2]_TXn– VSR[1–2]_TXn|. |VOD| is also referred to as output differential peak voltage. VTX-DIFFp-p = 2*|VOD|.
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