參數(shù)資料
型號(hào)： MSC8256SVT800B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783
文件頁(yè)數(shù)： 58/68頁(yè)
文件大小： 910K
代理商： MSC8256SVT800B
Hardware Design Considerations
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
61
3.5.1.4
DDR2 Unused MAPAR Pin Connections
When the MAPAR signals are not used, refer to Table 43 to determine the correct pin connections.
3.5.2
HSSI-Related Pins
3.5.2.1
HSSI Port Is Not Used
The signal names in Table 44 and Table 45 are generic names for a RapidIO interface. For actual pin names refer to Table 1.
3.5.2.2
HSSI Specific Lane Is Not Used
Table 43. Connectivity of MAPAR Pins for DDR2
Signal Name
Pin connection
MAPAR_OUT
NC
MAPAR_IN
NC
Notes:
1.
For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is used for DDR2.
2.
For MSC8256 Revision 1 silicon, these pins were connected to GND. For newer revisions of the MSC8256, connecting these
pins to GND increases device power consumption.
Table 44. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used
Signal Name
Pin Connection
SR_IMP_CAL_RX
NC
SR_IMP_CAL_TX
NC
SR[1–2]_REF_CLK
SXCVSS
SR[1–2]_REF_CLK
SXCVSS
SR[1–2]_RXD[3–0]
SXCVSS
SR[1–2]_RXD[3–0]
SXCVSS
SR[1–2]_TXD[3–0]
NC
SR[1–2]_TXD[3–0]
NC
SR[1–2]_PLL_AVDD
In use
SR[1–2]_PLL_AGND
In use
SXPVSS
In use
SXCVSS
In use
SXPVDD
In use
SXCVDD
In use
Note:
All lanes in the HSSI SerDes should be powered down. Refer to the MSC8256 Reference Manual for details.
Table 45. Connectivity of HSSI Related Pins When Specific Lane Is Not Used
Signal Name
Pin Connection
SR_IMP_CAL_RX
In use
SR_IMP_CAL_TX
In use
SR[1–2]_REF_CLK
In use
SR[1–2]_REF_CLK
In use
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