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| 型號： | MSC8256SVT800B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 52/68頁 |
| 文件大小： | 910K |
| 代理商： | MSC8256SVT800B |
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MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Hardware Design Considerations
Freescale Semiconductor
56
3.2
Each global PLL power supply must have an external RC filter for the PLLn_AVDD input (see Figure 37) in which the
following components are defined as listed:
R = 5
Ω ± 5%
C1 = 10 F
± 10%, 0603, X5R, with ESL
≤ 0.5 nH, low ESL Surface Mount Capacitor.
C2 = 1.0 F
± 10%, 0402, X5R, with ESL
≤ 0.5 nH, low ESL Surface Mount Capacitor.
Note:
A higher capacitance value for C2 may be used to improve the filter as long as the other C2 parameters do not change.
All three PLLs can connect to a single supply voltage source (such as a voltage regulator) as long as the external RC filter is
applied to each PLL separately. For optimal noise filtering, place the circuit as close as possible to its PLLn_AVDD inputs.
.
Each SerDes PLL power supply must be filtered using a circuit similar to the one shown in Figure 38, to ensure stability of the
internal clock. For maximum effectiveness, the filter circuit should be placed as closely as possible to the SRn_PLL_AVDD ball
to ensure it filters out as much noise as possible. The ground connection should be near the SRn_PLL_AVDD ball. The 0.003
μF
capacitor is closest to the ball, followed by the two 2.2
μF capacitors, and finally the 1 Ω resistor to the board supply plane. The
capacitors are connected from SRn_PLL_AVDD to the ground plane. Use ceramic chip capacitors with the highest possible
self-resonant frequency. All trances should be kept short, wide, and direct.
Figure 37. PLL Supplies
Figure 38. SerDes PLL Supplies
MSC8156E
PLL0_AVDD
R
C1
C2
PLL1_AVDD
R
C1
C2
PLL2_AVDD
R
C1
C2
VDD Power Rail
(Voltage Regulator)
VSS
1
Ω
2.2
μF
2.2
μF
0.003
μF
SRn_PLL_AVDD
SRn_PLL_AGND
as short as possible
GNDSXC
VDDSXC
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