參數(shù)資料
型號: MSM54V24632A
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 131,072-Word x 32-Bit x 2-Bank SGRAM without Graphics Functions
中文描述: 131,072字× 32位× 2,銀行SGRAM無圖形功能
文件頁數(shù): 3/29頁
文件大小: 401K
代理商: MSM54V24632A
3
Semiconductor
MSM54V24632A
PIN DESCRIPTION
CLK
CS
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM0, DQM1, DQM2 and DQM3.
CKE
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked that the subsequent CLK operation is deactivated.
CKE should be asserted at least one cycle prior to a new command.
Row & column multiplexed.
Row address: RA0 – RA8
Column address: CA0 – CA7
Selects bank to be activated during row address latch time and selects bank for precharge and read/
write during column address latch time. A9= "L" : Bank A, A9= "H" : Bank B
RAS
CAS
WE
DQM0
~DQM3
Functionality depends on the combination. For details, see the function truth table.
Masks the read data of two clocks later when DQM0~DQM3 is set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when DQM0~DQM3 is set "H" at the "H" edge of the clock signal.
Data inputs/outputs are multiplexed on the same pin.
Address
DQi
A9
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