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參數(shù)資料
| 型號： | MSM6242BGS-K |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封裝： | 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 6/24頁 |
| 文件大?。?/td> | 293K |
| 代理商： | MSM6242BGS-K |
OKI Semiconductor
MSM6242B
13/23
FEDL6242B-02
END
READ 30-SECOND
ADJ BIT
YES
NO
START
Figure 11 Writing 30-Second Adj. bit (Two Ways A, B)
125
s PASS?
30-SECOND
ADJ BIT = 0?
(A)
(B)
30-SECOND
ADJ BIT = 1
END
YES
NO
START
30-SECOND
ADJ BIT = 1
Table 2
0
1
0
1
Duty CYCLE of "0" level when
ITRPT/STND bit is "0".
0
1
1/64 second
1 second
1 minute
1 hour
Period
t1
t0
1/2
1/128
1/7680
1/460800
Figure 12
WRITE "0" INTO IRQ FLAG BIT
"INTERRUPT" DOES
NOT OCCUR BECAUSE
MASK BIT IS "1"
OPEN
LOW LEVEL
"INTERRUPT" TIMING
"0"
"1"
STD.P OUTPUT
MASK BIT
AUTOMATIC RETURN
OUTPUT DOES NOT OCCUR
AT LOW LEVEL BECAUSE
MASK BIT IS "1"
OPEN
LOW LEVEL
OUTPUT TIMING
"0"
"1"
STD.P
OUTPUT
MASK BIT
INTRT/STND BIT = "0"
INTRT/STND BIT = "1"
CE REGISTER (Control E Register)
a)
MASK (D0) –
This bit controls the STD.P output. When MASK = 1, then STD.P
= 1 (open); when MASK = 0, then STD.P = output mode. The
relationship between the MASK bit and STD.P output is shown
Figure 12.
b)
ITRPT/STND (D1) –
The ITRPT/STND input is used to switch the STD.P output
between its two modes of operation, interrupt and Standard
timing waveforms. When ITRPT/STND = 0 a fixed cycle wave-
form with a low-level pulse width of 7.8125 ms is present at the
STD.P output. At this time the MASK bit must equal 0, while the
period in either mode is determined by T0 (D2) and T1 (D3) of
Register E.
c)
T0 (D2), T1 (D3) –
These two bits determine the period of the STD.P output in both
interrupt and Fixed timing waveform modes. The tables below
show the timing associated with the T0, T1 inputs as well as their
relationship to INTRPT/STND and STD.P.
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