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參數(shù)資料
| 型號(hào)： | MSM6242BGS-K |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封裝： | 0.430 INCH, 1.27 MM PITCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 293K |
| 代理商： | MSM6242BGS-K |
OKI Semiconductor
MSM6242B
14/23
FEDL6242B-02
c)
24/12 (D2) –
This bit is for selection of 24/12 hour time modes. If D2 = 1–24 hour mode
is selected and the PM/AM bit is invalid. If D2 = 0–12 hour mode is
selected and the PM/AM bit is valid.
"24/HOUR/
Setting of the 24/12 hour bit is as follows:
12 HOUR"
1) REST bit = 1
2) 24/12 hour bit = 0 or 1
3) REST bit = 0
* REST bit must = 1 to write to the 24/12 hour bit.
d)
TEST (D3) –
When the TEST flag is a "1", the input to the SECONDS counter comes
from the counter/divider stage instead of the 15th divider stage. This
makes the SECONDS counter count at 5.4163 kHz instead of 1 Hz. When
TEST = 1 (Test Mode) the STOP & REST (Reset) flags do not inhibit internal
counting. When Hold = 1 during Test (Test = 1) internal counting is
inhibited; however, when the HOLD FLAG goes inactive (Hold = 0)
counter updating is not guaranteed.
STOP BIT
TIMING OF
"CARRY"
TO 8192 Hz
"CARRY" EXECUTED
"0"
"1"
"CARRY" NOT EXECUTED
"0"
"1"
Figure 13
(EXAMPLE) WHEN t1 = 1, t0 = 1 and MASK = 0.
PM12:00
WHEN ITRPT/STND
BIT is "1" STD.P OUTPUT
OPEN
LOW LEVEL
WHEN ITRPT/STND
BIT is "0"
PM1:00
OPEN
LOW LEVEL
The timing of the STD.P output designated by T1 and T0 occurs the moment that a carry occurs to a clock digit.
d)
The low-level pulse width of the fixed cycle waveform (ITRPT/STND = 0) is 7.8125 ms
independent of T0/T1 inputs.
e)
The fixed cycle waveform mode can be used for adjustment of the oscillator frequency time
base. (See Figure 14).
f)
During
±30 second adjustment a carry can occur that will cause the STD.P output to go low
when T0/T1 = 1, 0 or 1, 1. However, when T1/T0 = 0, 0 and ITRPT/STND = 0, carry does
not occur and the STD.P output resumes normal operation.
g)
The STD.P output is held (frozen) at the point at which STOP = 1 while ITRPT/STND = 0.
h)
No STD.P output change occurs as a result of writing data to registers S1 to H1.
C
F REGISTER (Control F Register)
a)
REST (D0) –
This bit is used to clear the clock's internal divider/counter of less than a
"RESET"
second. When REST = 1, the counter is Reset for the duration of REST. In
order to release this counter from Reset, a "0" must be written to the REST
bit. If CSI = 0 then REST = 0 automatically.
b)
STOP (D1) –
The STOP FLAG Only inhibits carries into the 8192 Hz divider stage.
There may be up to 122
s delay before timing starts or stops after
changing this flag; 1 = STOP/0 = RUN.
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