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MSM66573 Family User's Manual
Chapter 12 Serial Port Functions
12
Synchronous mode (SIO1)
[Master mode]
Figure 12-12 shows the timing diagram of operation during master mode transmission.
The clock pulse from the baud rate generator (timer 4) is divided by 4 to generate the
transmit shift clock.
In synchronization with the transmit shift clock that has been generated, the transmission
circuit controls transmission of the transmit data.
The S1BUF write signal (the signal that is output when an instruction to write to S1BUF is
executed, for example "STB A, S1BUF") acts as a trigger to start transmission.
One CPU clock after the write signal is generated, transmit data in S1BUF is set in the
transmit shift register. At this time, synchronized to the signal indicating the beginning of
an instruction (M1S1), a transmit buffer empty signal is generated.
After the transmit data is set (after the fall of the data transfer signal to the transmit shift
register), synchronized to the falling edge of the next transmit shift clock, the external output
clock begins to be output from the transmit clock I/O pin (TXC1). At the same time, transmit
data is output LSB first from the transmit data output pin (TXD1). Thereafter, as specified
by ST1CON and synchronized to the transmit shift clock, transmit data is output to complete
the transmission of one frame.
At this time, if the next transmit data has not been written to S1BUF, a transmit complete
signal is generated in synchronization with M1S1, and the transmission is completed.
TXD1 changes at the falling edge of TXC1. Therefore, at the receive side, TXD1 is fetched
at the rising edge of TXC1.
Because generation of the transmit shift clock is always unrelated to writes to S1BUF, from
the time when transmit data is written to S1BUF until the first data is output, there is a delay
of a maximum of 4 baud rate clocks.
Because SIO1 has S1BUF and the transmit shift register which are designed in a duplex
construction, during a transmission it is possible to write the next transmit data to S1BUF.
If S1BUF is written to during a transmission, after the current one frame transmission is
completed, the next transmit data will be automatically set in the transmit shift register, and
the data transmission will continue. After one frame of data is transmitted, if the next data
to be transmitted has been written to S1BUF, the transmit complete signal will not be
generated.
Figure 12-14 shows the timing diagram of operation during continuous transmission*.
[Note]
During continuous transmission, there is a time lag of 1 bit between the current data
transmission and the next data transmission, in which to set the next data. During this
interval, TXD1 is forced to a High level.