2-5
MSM66573 Family User's Manual
Chapter 2 CPU Architecture
2
(1)
Accessing program memory space
Program memory space is accessed by the program counter (PC) and the code segment
register (CSR). However, when a ROM table reference instruction (such as LC A, obj) or
a ROM window function (refer to Section 4.3) is executed, program memory space is
accessed according to the contents of the table segment register (TSR) and the register
specified by the instruction.
Access of the internal ROM area and the external memory area of the program memory
space is automatically switched by internal device operation depending on the status of the
EA pin.
When a high level is input to the
EA pin, the internal ROM area is accessed if the program
address is between 0000H and 0FFFFH, and the external ROM area is accessed if the
address is between 10000H and 0FFFFFH. When the external ROM area is accessed, the
secondary functions of the external memory control pins (ports 0, 1, 2, 3 and 4) must be set.
The area from 0000H to 0FFFDH can be fetched by the internal program. Therefore, be
careful that the final address of instruction code does not exceed 0FFFDH. The final
address of the table data is 0FFFFH.
When a low level is input to the
EA pin, the external program memory area is accessed for
all program addresses (0000H to 0FFFFFH).
If the external memory area of the program memory space is accessed, Port 0 (data input),
Port 4 (addresses A0 to A7 outputs), Port 1 (addresses A8 to A15 outputs) and Port 2
(addresses A16 to A19 outputs) operate as bus ports, and the P3_1/
PSEN pin becomes
active.
(2)
Vector table area
The 74-byte area of addresses from 0000H to 0049H and the 10-byte area of addresses
from 006AH to 0073H in segment 0 of program memory space are used as the vector table
area that stores branch addresses for all types of resets and interrupts (29 types) as shown
in Table 2-1.
If a reset or interrupt occurs, the corresponding 2-byte branch address, stored in the vector
table, is loaded into the PC. (The even address contains the lower order data and the odd
address contains the upper order data.) At the same time, "0" is loaded into the Code
Segment Register (CSR) and program execution starts from the loaded segment 0
address. Therefore if a reset or interrupt occurs during execution of an instruction in
segment 1 (or segment other than 0), program control will branch to an address in segment
0.
With reasons described above, reset routine and interrupt routines must be located in
segment 0. This fact is important for medium and large memory model programming.
Proper alignment attribute must be applied to your relocatable interrupt routines.
In medium and large memory model you specified by MEMSCON setting, CPU automatically
provides extra stack area for the CSR contents. When RTI instruction is executed, CSR
contents in stack are re-stored into CSR and program execution is continued in the same
program segment.
If this area is not used as a vector table area, it can be used as a normal program area.
Table 2-1 lists the vector table addresses for each type of reset or interrupt.