參數(shù)資料
型號(hào): MSM6789
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: SBC Solid-State Recorder IC
中文描述: 西南貝爾固態(tài)記錄器集成電路
文件頁(yè)數(shù): 34/53頁(yè)
文件大?。?/td> 813K
代理商: MSM6789
MSM6789A/6789L
Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Symbol
Type
Description
Mode Selection.
Low level : Stand-alone mode
High level : Microcontroller interface mode
A high input level causes the MSM6789A to be initialized and to go into the power
down state.
PDWN
I
Power Down.
When a low level is input the MSM6789A goes to the power down
state. Unlike the RESET pin, this pin does not force the MSM6789A to be reset.
When an Low level is applied to this pin during recording operation, the MSM6789A
is halted, and will be maintained in the power down state while
PDWN
is low level.
After this pin is restored to a high level, postprocessing for recording will be
performed.
RSEL1
RSEL2
I
I
MSEL2
L
L
L
L
L
L
L
L
MSEL1
L
L
L
L
H
H
H
H
RSEL2
L
L
H
H
L
L
H
H
RSEL1
L
H
L
H
L
H
L
H
Memory capacity
4M
1
4M
2
4M
3
4M
4
8M
1
8M
2
8M
3
8M
4
When serial register is selected (DRAM/
SR
= Low level)
MCUM
I
This pin selects
CAS
-before-
RAS
refresh period of DRAM at the time of
power down when DRAM is selected.
Low level : 15 μs max.
High level : 125 μs max.
LOWPWR
I
RESET
I
Bidirectional data bus to transfer commands and data to and from an external
microcontroller.
D0
D1
D2
D3
I/O
Write Pulse Input.
Inputting a low pulse to
WR
pin causes a command or data
to be input via D0 to D3 pins.
Read Pulse Input.
Inputting a low pulse to
RD
pin causes status bits or data to
be output via D0 to D3 pins.
Chip Enable Input.
When the
CE
pin is set to low level and the CE pin is set to a
high level, the write pulse (
WR
) or read pulse (
RD
) can be accepted.
When the
CE
pin is set to a high level or CE pin is set to a low level, the write pulse
(
WR
) and read pulse (
RD
) cannot be accepted so that data cannot be communicated
via D0 to D3 pins.
WR
I
RD
I
CE
CE
I
Pin
60
56
57
34
87
62
24
25
26
27
63
64
65
35
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