參數(shù)資料
型號(hào): MSM6789
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: SBC Solid-State Recorder IC
中文描述: 西南貝爾固態(tài)記錄器集成電路
文件頁(yè)數(shù): 8/53頁(yè)
文件大?。?/td> 813K
代理商: MSM6789
MSM6789A/6789L
Semiconductor
PIN DESCRIPTIONS (for MSM6789A (5 V Version)) (Continued)
Symbol
Type
Description
Mode Selection.
Low level : Stand-alone mode
High level : Microcontroller interface mode
A high input level causes the MSM6789A to be initialized and to go into the power
down state.
PDWN
I
Power Down.
When a low level is input, the MSM6789A goes to the power down
state. Unlike the RESET pin, this pin does not force the MSM6789A to be reset.
When a Low level is applied to this pin during recording operation, the MSM6789A
is halted, and will be maintained in the power down state while
PDWN
is low level.
After this pin is restored to a high level, postprocessing for recording will be performed.
Oscillator Connection.
When an external clock is used, input the clock through
this pin. During the power down state, this pin must be set to the ground level.
Oscillator Connection.
When an external clock is used, this pin must be left
open.
XT
I
TEST
TEST
TMD3-TMD0
TDT7-TDT0
SYNC
TDT3-TDT0
[DQ4]-[DQ1]
TST
TCK
TMD4
MSM6789A Test.
Input a low level to the TEST pin and a high level to the
TEST
pin.
RSEL1
RSEL2
I
I
I
MSEL2
L
L
L
L
L
L
L
L
MSEL1
L
L
L
L
H
H
H
H
RSEL2
L
L
H
H
L
L
H
H
RSEL1
L
H
L
H
L
H
L
H
Memory capacity
4M
1
4M
2
4M
3
4M
4
8M
1
8M
2
8M
3
8M
4
When serial register is selected (DRAM/
SR
= Low level)
MCUM
I
XT
O
MSM6789A Test.
This pin must be left open.
I/O
Connect these pins to DQ1-DQ4 of DRAM at the time of 4-bit
type DRAM
selection. Otherwise these pins must be left open as they are MSM6789A test pins.
I/O
MSM6789A Test.
Input a low level signal.
I
This pin selects
CAS
-before-
RAS
refresh period of DRAM at the time of
power down when DRAM is selected.
Low level : 15 μs max.
High level : 125 μs max.
LOWPWR
I
RESET
I
Pin
60
91
56
57
37
61
34
92
9-12
13-20
21
17-20
22
23
8
87
62
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