參數(shù)資料
型號(hào): MSM7581
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: ITU-T G.721 4ch ADPCM TRANSCODER
中文描述: ITU - T的G.721 4路差分PcM碼器
文件頁(yè)數(shù): 12/18頁(yè)
文件大小: 165K
代理商: MSM7581
12/18
Semiconductor
MSM7581
THR Processing Timing
Timing Block Diagrams, when CODER and DECODER output data, are shown in the following
figures.
The parallel to serial conversion of the output unit employs a load format and the load point is
at the rising edge of a synchronous signal.
Therefore, input THR signal with respect to SYXA for CODER with timing of satisfying ts and
th conditions shown in the figure.
For DECODER, THR signal should be input even of through-data is input.
The input timing should satisfy the conditions shown in the following figures.
CODER
8
Through-data
4b
ADPCM
CODER
8b
S
E
L
SYNCA
SOA
BCLKA
Serial
Parallel
SYXP
SIP
BCKP
THR
Latch timing=A
MSB
LSB
th
ts
MSB
ts=100ns or more
th=100ns or more
PCM side SYNC (SYXP)
PCM Input (SIP)
Internal Latch timing (A)
Internal Input Data
ADPCM side SYNC (SYXA)
Through-data Output (SOA)
BCKA
THR
Through-data
Parallel
Serial
Latch
Note:
That data-ship may occur when the rising edge (data load point) of SYXA and input of
the internal latch timing overlap each other.
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