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參數(shù)資料
| 型號(hào)： | MSM7581 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | ITU-T G.721 4ch ADPCM TRANSCODER |
| 中文描述： | ITU - T的G.721 4路差分PcM碼器 |
| 文件頁(yè)數(shù)： | 5/18頁(yè) |
| 文件大?。?/td> | 165K |
| 代理商： | MSM7581 |
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Semiconductor
MSM7581
THR1, THR2, THR3, THR4
Control pins for the data-through modes.
THR (1 - 4) are for Channel (1 - 4), respectively. The data-through mode is selected when digital
“1” is applied to THR (1 - 4). In this mode, 8-bit serial input data applied to SIA (1 - 4) (ADPCM
data input) is passed to the PCM serial data output pins, SOP (1 - 4), without any data
modification. SOP (1 - 4) go to the high impedance state after the output of 8-bit data has been
applied to SIA (1 - 4).
Conversely 8-bit serial input data applied to SIP (1 - 4) (PCM data input) is passed to ADPCM
serial data output pins, SOA (1 - 4), without any data modification.
SOA (1 - 4) go to the high impedance state after the output of 8-bit serial data has been applied
to SIP (1 - 4).
ADPCM and PCM data interfaces have the mutually independent signal input pins for
synchronizing signals. The time slots for data input and output can be exchanged between them.
Some timing at which data may be deleted or duplicated as described in "Note on Usage" should
not be used.
SYXP1 - 4, SYRP1 - 4
Synchronous signal input pins to define PCM data input and output timing for Channel 1 (SIP1,
SOP1), Channel 2 (SIP2, SOP2), Channnel 3 (SIP3, SOP3), and Channel 4 (SIP4, SOP4).
The synchronous signals SYXA1 and SYRAI (Channel 1), SYXA2 and SYRA2 (Channel 2),
SYXA3 and SYRA3 (Channel 3), and SYXA4 and SYRA4 (Channel 4), which define ADPCM data
input and output timing are provided.
PCM and ADPCM data interfaces can be used at a mutually independent timing except some
timing.
Note: When PCM and ADPCM data interfaces are used at a mutually independent timing, the
timing described in "Note on Usage" should not be used.
SYXP signals must be input for PAD signal input processing.
BCKP1 - 4
Bit clock input.
These signals define the PCM data transmission speed at the PCM data input/output terminals.
BCKP (1 - 4) are used for Channel (1 - 4). Since BCKA (1 - 4) defines the data rate of the ADPCM
data interface, the PCM and ADPCM data can be input or output at different speeds.
LAW
PCM data companding law selection.
Digital “1” and “0” correspond to A-law and
μ
-law, respectively.
PDN1
,
PDN2
,
PDN3
,
PDN4
Power down mode selection.
PDN1 - 4
can be independently set to power down mode. When digital “0” is applied, these pins
are in the power-down mode.
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| MSM7582 | 制造商:OKI 制造商全稱(chēng):OKI electronic componets 功能描述:pie/4 Shift QPSK MODEM |
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| MSM7584C | 制造商:OKI 制造商全稱(chēng):OKI electronic componets 功能描述:pi /4 Shift QPSK MODEM/ADPCM CODEC |
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