參數(shù)資料
型號(hào)： MSM7661
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： NTSC/PAL Digital Dencoder(NTSC/PAL制式數(shù)字譯碼器)
中文描述： NTSC / PAL數(shù)字Dencoder（的NTSC / PAL制式數(shù)字譯碼器）
文件頁(yè)數(shù)： 28/40頁(yè)
文件大?。?/td> 293K
代理商： MSM7661
Semiconductor
MSM7661
28/40
OPERATION MODE SETTING
The video mode includes ;
1. Internal terminal mode to be directly set by a dedicated terminal
2. Register setting mode to be specified by setting the internal registers
These modes can be changed by the mode register MRA [4].
The reset state (default) is the external terminal mode.
The following registers can be set in the external terminal mode.
MRA[3]
input signal mode
*0:
1:
Composite video input
S-video input
MRA[2 : 0]
input mode
*000:
001:
010:
100:
101:
NTSC ITU-R601
NTSC Square Pixel
MTSC 4Fsc
PAL ITU-R601
PAL Square Pixel
13.5 MHz
12.27 MHz
14.31818 MHz
13.5 MHz
14.75 MHz
OPERATION CLOCK SETTING
The operation clock settings at ITU-R601 are shown below.
Input clock
27.0 MHz
27.0 MHz
13.5 MHz
Input data
27.0 MHz
13.5 MHz
13.5 MHz
CLKSEL Pin
"L"
"L"
"H"
Register (MRB2)
"0" (decimation filter used)
"1" (Unused)
"1" (Unused)
Clock for A/D converter
CLKX2O (27 MHz)
CLKXO (13.5 MHz)
CLKX2O or CLKXO (13.5 MHz)
When the double speed clock is used, data can be input at a double speed or at an ordinary speed
by setting the internal register (MRB2) and the clock for the A/D converter.
The internal processing after decimation filter is performed at an ordinary speed.
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