參數(shù)資料
型號: MSM7661
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: NTSC/PAL Digital Dencoder(NTSC/PAL制式數(shù)字譯碼器)
中文描述: NTSC / PAL數(shù)字Dencoder(的NTSC / PAL制式數(shù)字譯碼器)
文件頁數(shù): 4/40頁
文件大?。?/td> 293K
代理商: MSM7661
Semiconductor
MSM7661
4/40
PIN DESCRIPTIONS
Pin
1 to 8
9 to 16
17
18
19
20
21 to 24
26
27
28
29
30
31
32
Type
I
I
I
I/O
I
I
I
I
I
I
Symbol
CD[0 to 7]
CVBS[0 to 7]
V
DD
GND
SCL
SDA
MODE[0 to 3]
PLLSEL
25
I
RESET_L
CLKSEL
TEST1
SLEEP
TE
GND
V
DD
Description
Chrominance signal input pin (valid only for S video input)
Set each pin to "L" level at composite signal input.
Composite signal input pin
Luminance signal is input for S video input.
I
2
C-bus clock pin
I
2
C-bus data pin
Mode input pins. These pins are internally pulled-down.
MODE[3]
0: composite
1: S video
MODE[1:0]
00: ITU-R601
01: Square Pixel
10: 4Fsc (only for NTSC)
11: none
If ITU-R signals are input when registers are set to automatic NTSC/PAL
recognition mode, NTSC/PAL is automatically recognized irrespective of
MODE2 setting.
System reset pin (active at "L")
Unused.
Fixed to "H" externally.
Clock select input pin.
"L"
double-speed 27 MHz, "H"
ordinary 13.5 MHz
Input pin for testing. Normally "L". Internally pulled down.
Sleep mode setting pin. Normally "L". Internally pulled down.
Input pin for testing. Normally "L". Internally pulled down.
MODE[2]
0: NTSC
1: PAL
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