參數(shù)資料
型號(hào)： MSM7712
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： Wireless LAN Baseband Controller
中文描述： 無(wú)線局域網(wǎng)的基帶控制器
文件頁(yè)數(shù)： 11/20頁(yè)
文件大?。?/td> 157K
代理商： MSM7712
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MSM7712
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11
Oki Semiconductor
SYNCLK, SYNDAT,
SYNLEN
Open collector
These signals provide the interface to the radio synthesizer to select the transmit/receive carrier.
Many synthesizers are supported by a flexible architecture. The data is output on SYNDAT ready
for the rising edge of SYNCLK. SYNLEN is asserted during the programming, and the data is
latched on the rising edge of SYNCLEN. SYNCLK is clocked at RCK divided by 2.
SYNCLK and SYNDAT are also used to program a serial DAC used for TX power control, CCA
threshold and RSSI measurement (see below). The synthesizer is programmed when the radio
is idle. The RSSI and CCA threshold DAC is used at the start of receiving a packet. The TX power
DAC is programmed at the start of transmitting packet.
The radio provides indication of being in lock with LKDET. This input is active high or low (pro-
grammable), pulse sensitive, and latched so that both pulsed and steady out-of-lock signals are
recognized. Glitches shorter than 2 RCK periods are ignored. Transmission is prevented when
the synthesizer is out-of-lock
LKDET
Input
DACEN
Open-collector
For TX power control, CCA threshold and RSSI measurement, data is also clocked into a serial
DAC (10/12 bit type e.g. MAX515/MAX539) using the SYNCLK and SYNDAT lines as described
above, except that DACEN is asserted during the programming, and the data is latched on the
rising edge of DACEN.
RSSITH is an input from a threshold comparison of the analog RSSI signal from the radio with
the DAC output. It is high when the received signal exceeds the programmed threshold. This
performs two purposes:
A minimum threshold of RSSI can be set before enabling the demodulator for CCA to reduce
power.
Once a valid receive signal is determined (CCA invalid) the RSSI can be measured with the
external comparator/DAC and a SAR within the MSM7712. The RSSI measurement is
performed for internal and external modem options when CCA is determined.
The same DAC can be used for both TX power control, RSSI threshold and RSSI measurement
RSSITH
Input
RCK
Output
A clock to the radio is provided on this pin. The clock is derived from SCK when RADPWR is
asserted, with fixed division ratio of one or two (selected by post-reset configuration
SCK_CONF). RCK is typically 16MHz for the radio synthesizer reference.
Radio Interface Signal Descriptions
(Continued)
Pin Name
Direction
Description
Figure 5. Connection of Serial DAC for Power Control and RSSI
RSSITH
DACEN
SYNDAT
SYNCLK
-
+
D
CSN
DAC
Radio
MSM7712
Power Control
Analog RSSI
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