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參數資料
| 型號： | MSM7712 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Wireless LAN Baseband Controller |
| 中文描述： | 無線局域網的基帶控制器 |
| 文件頁數： | 16/20頁 |
| 文件大小： | 157K |
| 代理商： | MSM7712 |
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MSM7712
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16
Oki Semiconductor
AC Characteristics
Processor Interface
The MSM7712 is designed to operate with the V80C86, V33, V53A, and 80C186 processors. Refer to the
appropriate processor data sheets for detailed information.
Host Interface
The MSM7712 meets the timing requirements of the PCMCIA interface. Wait states are used to provide
the access times to the shared RAM when required.
Shared Memory Interface
Shared Memory Timing
[1]
The shared memory cycle time is 2 RCK clock periods. When the memory interface is not active the data
bus RD[15:0] is output (low). This ensures the shared memory data bus does not float and consume
power.
1.
RCK at 16 MHz.
Parameter
Description
Min.
Typ.
Max.
Unit
t
S(RCE)
t
H(RCE)
t
RCE
t
S(D-CE)
t
ACC
t
H(RCE-D)
t
H(CYC)
Setup time of address, WR strobe and data output to RCE asserted
20
-
-
ns
Hold time of address, WR strobe and data output to RCE deasserted
10
-
-
RCE low period (with 16/32 MHz SCK)
85
-
-
Setup time of read data to RCE deasserted
10
-
-
RAM access time Tce -Ts (d-rce)
75
-
-
Hold time of read data to RCE deasserted
0
-
-
Hold time before data bus driven low
50
-
70
Figure 6. Shared Memory Timing
RA[], RWRN
RCEHN, RCELN
RD[], READ
RD[], WRITE
T
S(RCE)
T
RCE
T
B(RCE)
T
S(D-RCE)
T
H(RCE-D)
T
H(CYC)
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