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參數資料
| 型號： | MSM7712 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | Wireless LAN Baseband Controller |
| 中文描述： | 無線局域網的基帶控制器 |
| 文件頁數： | 17/20頁 |
| 文件大?。?/td> | 157K |
| 代理商： | MSM7712 |
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I
MSM7712
I
17
Oki Semiconductor
E
2
PROM Interface
Radio Control Timing
The following diagram shows a typical receive-transmit-receive sequence. RXPHE is asserted for receive.
When CSENSE is detected(1) a packet is received. When CSENSE is inactive a transmit is requested by
TXPHYE asserted. Delays between the receive control pins RXCx and transmit control pins TXCx are
programmable to suit different radio designs. The packet is transmitted and when no further information
is to be transmitted TXPHYE is deasserted. The modem holds CSENSE (2) until the ramp down is com-
plete when the transmit control pins are deasserted and receive control pins are asserted. Note: RXPHYE,
TXPHYE and CSENSE are internal signals.
Radio Control Timing
[1]
1.
RCK at 16 MHz.
E
2
PROM Timing
[1]
Parameter
Description
Min.
Typ.
Max.
Symbol
t
SKL
t
SKH
t
SU
t
S(DO-SK)
t
H(SK-DO)
Clock low time
-
2000
-
ns
Clock high time
-
2000
-
CS,DI setup time to rising clock
-
2000-125
-
Setup time of read data to rising clock
10
-
-
Hold time of read data to rising clock
0
-
-
Parameter
Description
Min.
Typ.
Max.
Symbol
t
ONRT1
t
ONTIT2
t
ONT1IF
t
OFFCST2
t
OFFT2T1
t
OFFT1R
RXC1 deasserted to TXC1 asserted
0
3000
7000
ns
TXC1 asserted to TXC2 asserted
0
2000
7000
TXC2 asserted to IF data output
0
2000
15000
CSENSE deasserted to TXC2 deasserted
0
5
20
TXC2 deasserted to TXC1 deasserted
0
4000
7000
TXC1 deasserted to RXC1 asserted
0
1000
7000
Figure 7. E
2
PROM Timing
EECS
EESK
EEDI
EEDO
t
SKI
t
S(DO-SK)
t
H(SK-DO)
t
SKH
t
SU
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