參數(shù)資料
型號(hào)： MSM80C88A-10GS-K
廠商： OKI ELECTRIC INDUSTRY CO LTD
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56
封裝： 15 X 19 MM, 1 MM PITCH, PLASTIC, QFP-56
文件頁(yè)數(shù)： 16/37頁(yè)
文件大小： 267K
代理商： MSM80C88A-10GS-K
23/37
Semiconductor
MSM80C88A-10RS/GS/JS
EXTERNAL INTERFACE
Reset
CPU initialization is executed by the RESET pin. The MSM80C88A-10’s RESET High signal is
required for greater than 4 clock cycles.
The rising edge of RESET terminates the present operation immediately. The falling edge of
RESET triggers an internal reset sequence for approximately 10 clock cycles. After internal reset
sequence is finished, normal operation begins from absolute location FFFF0H.
Interrupt Operations
The interrupt operation is classified as software or hardware, and hardware interrupt is
classified as non-markable or maskable.
An interrupt causes a new program location which is defined by the interrupt pointer table,
according to the interrupt type. Absolute location 00000H through 003FFH is reserved for the
interrupt pointer table. The interrupt pointer table consists of 256-elements. Each element is 4
bytes in size and corresponds to an 8-bit type number which is sent from an interrupt request
device during the interrupt acknowledge cycle.
Non-maskable Interrupt (NMI)
The MSM80C88A-10 has a non-maskable interrupt (NMI) which is of higher priority than a
maskable interrupt request (INTR).
An NMI request pulse width needs minimum of 2 clock cycles. The NMI will be serviced at the
end of the current instruction or between string manipulations.
Maskable Interrupt (INTR)
The MSM80C88A-10 provides another interrupt request (INTR) which can be masked by
software. INTR is level triggerd, so it must be held until interrupt request is acknowledged.
The INTR will be serviced at the end of the current instruction or between string manipulations.
Interrupt Acknowledge
During the interrupt acknowledge sequence, further interrupts are disabled. The interrupt
enable bit is reset by any interrupt, after which the Flag register is automatically pushed onto
the stack. During an acknowledge sequence, the CPU emits the lock signal from T2 of first bus
cycle to T2 of second bus cycle. At the second bus cycle, a byte is fetched from the external device
as a vector which identifies the type of interrupt. This vector is multiplied by four and used as
an interrupt pointer address (INTR only).
The interrupt Return (IRET) instruction includes a Flag pop operation which returns the
original interrupt enable bit when it restores the Flag.
相關(guān)PDF資料
PDF描述
MSM81C55-5GS-2K 22 I/O, PIA-GENERAL PURPOSE, PQFP44
MSM82C51A-2GS-VK 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32
MSM82C51A-2JS 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PQCC28
MSM82C51A-2GS-K 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32
MSM82C53-2GS-K 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSM80C88A-10JS 制造商:OKI 制造商全稱(chēng):OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR
MSM80C88A-10RS 制造商:OKI 制造商全稱(chēng):OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR
MSM80C88A2JS 制造商:OKI 功能描述:*
MSM8128 制造商:MOSAIC 制造商全稱(chēng):MOSAIC 功能描述:128K x 8 SRAM
MSM8128V-10 制造商:MOSAIC 制造商全稱(chēng):MOSAIC 功能描述:128K x 8 SRAM
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