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參數(shù)資料
| 型號(hào)： | MSM80C88A-10GS-K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56 |
| 封裝： | 15 X 19 MM, 1 MM PITCH, PLASTIC, QFP-56 |
| 文件頁數(shù)： | 7/37頁 |
| 文件大?。?/td> | 267K |
| 代理商： | MSM80C88A-10GS-K |
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Semiconductor
MSM80C88A-10RS/GS/JS
PIN DESCRIPTION
AD0 - AD7
ADDRESS DATA BUS: Input/Output
These lines are the multiplexed address and data bus.
These are the address bus at T1 cycle and the data bus at T2, T3, TW and T4 cycle.
T2, T3, TW and T4 cycle.
These lines are high impedance during interrupt acknowledge and hold acknowledge.
A8 - A15
ADDRESS BUS: Output
These lines are the address bus bits 8 thru 15 at all cycles.
These lines do not have to be latched by an ALE signal.
These lines are high impedance during interrupt acknowledge and hold acknowledge.
A16/S3, A17/S4, A18/S5, A19/S6
ADDRES/STATUS : Output
These are the four most significant address as at the T1, cycle.
Accessing I/O port address, these are low at T1 Cycle.
These lines are Status lines at the T2, T3, TW and T4 Cycles.
S5 indicates interrupt enable Flag.
S3 and S4 are encoded as shown below.
These lines are high impedance during hold acknowledge.
RD
READ: Output
This line indicates that CPU is in a memory or I/O read cycle.
This line is the read strobe signal when CPU reads data from a memory or I/O device. This
line is active low.
This line is high impedance during hold acknowledge.
READY
READY:Input
This line indicates to the CPU that the addressed memory or I/O device is ready to read or
write.
This line is active high. If the setup and hold time are out of specification, an illegal operation
will occur.
INTR
INTERRUPT REQUEST: Input
This line is the level triggered interrupt request signal which is sampled during the last clock
cycle of instruction and string manipulations.
It can be internally masked by software.
This signal is active high and internally synchronized.
1
0
1
Stack
0
Alternate Data
S3
0
1
0
S4
Characteristics
Code or None
Data
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM81C55-5GS-2K | 22 I/O, PIA-GENERAL PURPOSE, PQFP44 |
| MSM82C51A-2GS-VK | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32 |
| MSM82C51A-2JS | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PQCC28 |
| MSM82C51A-2GS-K | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32 |
| MSM82C53-2GS-K | 3 TIMER(S), PROGRAMMABLE TIMER, PDSO32 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM80C88A-10JS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR |
| MSM80C88A-10RS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:8-Bit CMOS MICROPROCESSOR |
| MSM80C88A2JS | 制造商:OKI 功能描述:* |
| MSM8128 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM |
| MSM8128V-10 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM |
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