參數(shù)資料
型號(hào): MSM80C88A-10GS-K
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56
封裝: 15 X 19 MM, 1 MM PITCH, PLASTIC, QFP-56
文件頁(yè)數(shù): 17/37頁(yè)
文件大小: 267K
代理商: MSM80C88A-10GS-K
24/37
Semiconductor
MSM80C88A-10RS/GS/JS
HALT
When a Halt instruction is executed, the CPU enters Halt state. An interrupt request or RESET
will force the MSM80C88A-10 out of the Halt state.
System Timing – Minimum Mode
A bus cycle begins at T1 with an ALE signal. The trailing edge of ALE is used to latch the address.
From T1 to T4 the IO/M signal indicates a memory or I/O operation. From T2 to T4, the address
data bus changes the address but to the data bus.
The read (RD), write (WR), and interrupt acknowledge (INTA) signals caused the addressed
device to enable the data bus. These signals become active at the beginning of T2 and inactive
at the beginning of T4.
System Timing – Maximum Mode
In maximum mode, the MSM82C88-2 Bus Controller is added to system. The CPU sends status
information to the Bus Controller. Bus timing signals are generated by the Bus Controller. Bus
timing is almost the same as in minimum mode.
Interrupt Acknowledge Sequence
ALE
LOCK
INTA
AD0 - AD7
T1
T2
T3
T4 TI
T1
T2
T3
T4
Type Vector
Float
相關(guān)PDF資料
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