參數(shù)資料
型號(hào): MSM80C88A-10GS-K
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56
封裝: 15 X 19 MM, 1 MM PITCH, PLASTIC, QFP-56
文件頁(yè)數(shù): 5/37頁(yè)
文件大小: 267K
代理商: MSM80C88A-10GS-K
13/37
Semiconductor
MSM80C88A-10RS/GS/JS
Maximum Mode (continued)
Notes: 1. All signals switch between VOH and VOL unless otherwise specified.
2. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to
be inserted.
3. Cascade address is valid between first and second INTA cycle.
4. Two INTA cycles run back-to-back. The MSM80C86A-10 LOCAL ADDR/DATA
BUS is floating during both INTA cycles. Control for pointer address is shown for
second INTA cycle.
5. Signal at MSM82C84A-2 or MSM82C88-2 shown for reference only.
The issuance of the MSM82C88-2 command and control signals (MRDC, MWTC,
AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high MSM82C88-2
CEN.
7. All timing measurements are made at 1.5 V unless otherwise noted.
8. Status inactive in state just prior to T4.
VIH
VIL
AD7 - AD0
A15 - A8
(See NOTES 3 & 4)
CLK (MSM82C84A-2 Outputs)
S2, S1, S0 (Except Halt)
MSM82C88-2 Outputs
See NOTES 5, 6
MSM82C88-2 Outputs
See NOTES 5, 6
INTA Cycle
tCHSV
T1
DEN
ANMC or AIOWC
MWTC or IOWC
MCE/
PDEN
AD7 - AD0
DT/R
INTA
DEN
Write Cycle
AD7 - AD0, A15 - A8
S2, S1, S0
Software Halt
(DEN VOL; RD, MRDC, IORC, MWTC, AMWC,
IOWC, AIOWC, INTA VOH)
tCLAV
tCLSH
tCLAX
tCLDV
tCVNX
tCLML
tCLMH
tCLML
tCLMH
tDVCL
tCLDX
tCHDTH
tCLMH
tCVNX
tCVNV
tCLAV
tCLML
tCHDTL
tCLMCH
tSVMCH
tCVNX
tCLAZ
tCVNV
Data
(See
NOTE 8)
Pointer
Float
Reserved for
Cascade ADDR
Float
AD7 - AD0
T2
T3
Tw
T4
Invalid Address
tCHDX
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