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參數(shù)資料
| 型號： | MSM80C88A-10RS |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 10 MHz, MICROPROCESSOR, PDIP40 |
| 封裝： | 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 10/37頁 |
| 文件大?。?/td> | 267K |
| 代理商： | MSM80C88A-10RS |
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Semiconductor
MSM80C88A-10RS/GS/JS
ALE
ADDRESS LATCH ENABLE: Output
This line is used for latching an address into the MSM82C12 address latch it is a positive pulse
and the trailing edge is used to strobe the address. This line is never floated.
DT/R
DATA TRANSMIT/RECEIVE: Output
This line is used to control the direction of the bus transceiver.
When this line is high, the CPU transmits data, and when it is low. the CPU receives data.
This line is high impedance during hold acknowledge.
DEN
DATA ENABLE: Output
This line is used to control the output enable of the bus transceiver. This line is active low. This
line is high impedance during hold acknowledge.
HOLD
HOLD REQUEST: Input
This line is used for a Bus Request from an other device.
This line is active high.
HLDA
HOLD ACKNOWLEDGE: Output
This line is used for a Bus Grant to an other device.
This line is active high.
SS0
STATUS: Output
This line is logically equivalent to S0 in the maximum mode.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM80C88A-10JS | 8-BIT, 10 MHz, MICROPROCESSOR, PQCC44 |
| MSM80C88A-10GS-K | 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56 |
| MSM81C55-5GS-2K | 22 I/O, PIA-GENERAL PURPOSE, PQFP44 |
| MSM82C51A-2GS-VK | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32 |
| MSM82C51A-2JS | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM80C88A2JS | 制造商:OKI 功能描述:* |
| MSM8128 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM |
| MSM8128V-10 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM |
| MSM8128V-12 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM |
| MSM8128V-70 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM |
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