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參數(shù)資料
| 型號： | MSM80C88A-10RS |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 10 MHz, MICROPROCESSOR, PDIP40 |
| 封裝： | 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40 |
| 文件頁數(shù)： | 37/37頁 |
| 文件大?。?/td> | 267K |
| 代理商： | MSM80C88A-10RS |
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Semiconductor
MSM80C88A-10RS/GS/JS
Timing Responses
Parameter
Symbol
Unit
Max.
Min.
10 MHz Spec.
VCC = 4.75 V to 5.25 V
Ta = 0 to +70°C
Max.
Min.
8 MHz Spec.
VCC = 4.75 V to 5.25 V
Ta = 0 to +70°C
Max.
Min.
5 MHz Spec.
VCC = 4.5 V to 5.5 V
Ta = –40 to +85°C
Command Active Delay (See Note 1)
tCLML
535
ns
Command Inactive Delay (See Note 1)
tCLMH
545
ns
READY Active to Status Passive
(See Note 4)
tRYHSH
—45
ns
535
545
—65
5
45
5
45
—
110
Status Inactive Delay
Status Active Delay
tCHSV
10
45
ns
10
60
10
110
Address Valid Delay
tCLSH
10
60
ns
10
70
10
130
Address Hold Time
tCLAV
10
60
ns
10
60
10
110
Address Float Delay
tCLAX
10
—
ns
10
—
10
—
Status Valid to ALE High (See Note 1)
tCLAZ
tCLAX
50
ns
tCLAX
50
tCLAX
80
Status Valid to MCE High (See Note 1)
tSVLH
—25
ns
—25
—
35
CLK Low to ALE Valid (See Note 1)
tSVMCH
—30
ns
—30
—
35
CLK Low to MCE High (See Note 1)
tCLLH
—25
ns
—25
—
35
ALE Inactive Delay (See Note 1)
tCLMCH
—25
ns
—25
—
35
Data Valid Delay
tCHLL
425
ns
425
4
35
Data Hold Time
tCLDV
10
60
ns
10
60
10
110
tCHDX
10
—
ns
10
—
10
—
Control Active Delay (See Note 1)
tCVNV
545
ns
Control Inactive Delay (See Note 1)
tCVNX
545
ns
545
5
45
5
45
RD Active Delay
Address Float to RD Active
tAZRL
0—
ns
0—
0
—
RD Inactive Delay
tCLRL
10
70
ns
10
100
10
165
RD Inactive to Next Address Active
tCLRH
10
60
ns
10
80
10
150
tRHAV
tCLCL-35
—
ns
tCLCL-40
—
tCLCL-45
—
tCHDTL
—50
ns
—50
—
50
GT Active Delay (See Note 5)
GT Inactive Delay
tCLGL
045
ns
050
0
85
RD Width
tCLGH
045
ns
050
0
85
Output Rise Time (From 0.8 V to 2.0 V)
tRLRH
2tCLCL-40
—ns
2tCLCL-50
—
2tCLCL-75
—
Output Fall Time (From 2.0 V to 0.8 V)
tOLOH
—15
ns
—15
—
15
tOHOL
—15
ns
—15
—
15
Direction Control Active Delay
(See Note 1)
tCHDTH
—30
ns
—30
—
35
Direction Control Inactive Delay
(See Note 1)
Notes: 1. Signals at MSM82C84A-2 or MSM82C88-2 are shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next
CLK.
3. Applies only to T2 state (8 ns into T3)
4. Applies only to T3 and wait states.
5. CL = 40 pF (RQ/GT0, RQ/GT1)
相關PDF資料 |
PDF描述 |
|---|---|
| MSM80C88A-10JS | 8-BIT, 10 MHz, MICROPROCESSOR, PQCC44 |
| MSM80C88A-10GS-K | 8-BIT, 10 MHz, MICROPROCESSOR, PQFP56 |
| MSM81C55-5GS-2K | 22 I/O, PIA-GENERAL PURPOSE, PQFP44 |
| MSM82C51A-2GS-VK | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PDSO32 |
| MSM82C51A-2JS | 1 CHANNEL(S), 64K bps, SERIAL COMM CONTROLLER, PQCC28 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MSM80C88A2JS | 制造商:OKI 功能描述:* |
| MSM8128 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM |
| MSM8128V-10 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM |
| MSM8128V-12 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM |
| MSM8128V-70 | 制造商:MOSAIC 制造商全稱:MOSAIC 功能描述:128K x 8 SRAM |
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