參數(shù)資料
型號: MSM80C88A-10RS
廠商: OKI ELECTRIC INDUSTRY CO LTD
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 10 MHz, MICROPROCESSOR, PDIP40
封裝: 0.600 INCH, 2.54 MM PITCH, PLASTIC, DIP-40
文件頁數(shù): 35/37頁
文件大小: 267K
代理商: MSM80C88A-10RS
7/37
Semiconductor
MSM80C88A-10RS/GS/JS
Timing Responses
RD Inactive Delay
tCLRH
10
60
ns
RD Inactive to Next Address Active
tRHAV
tCLCL-35
ns
HLDA Valid Delay
tCLHAV
10
60
ns
10
80
tCLCH-40
10
100
10
150
tCLCH-45
10
160
RD Width
tRLRH
2tCLCL-40
ns
2tCLCL-50
2tCLCL-75
WR Width
tWLWH
2tCLCL-35
ns
2tCLCL-40
2tCLCL-60
Address Valid to ALE Low
tAVAL
tCLCH-35
ns
tCLCH-40
tCLCH-60
Ouput Rise Time (From 0.8 V to 2.0 V) tOLOH
—15
ns
—15
15
Output Fall Time (From 2.0 V to 0.8 V)
tOHOL
—15
ns
—15
15
Parameter
Symbol
Unit
Max.
Min.
10 MHz Spec.
VCC = 4.75 V to 5.25 V
Ta = 0 to +70°C
Max.
Min.
8 MHz Spec.
VCC = 4.75 V to 5.25 V
Ta = 0 to +70°C
Max.
Min.
5 MHz Spec.
VCC = 4.5 V to 5.5 V
Ta = –40 to +85°C
Address Valid Delay
tCLAV
10
60
ns
Address Hold Time
tCLAX
10
ns
Address Float Delay
tCLAZ
tCLAX
50
ns
10
60
10
tCLAX
50
10
110
10
tCLAX
80
ALE Width
tLHLL
tCLCH-10
ns
tCLCH-10
tCLCH-20
ALE Active Delay
tCLLH
—40
ns
—50
80
ALE Inactive Delay
tCHLL
—45
ns
—55
85
Address Hold Time to ALE Inactive
tLLAX
tCLCH-10
—ns
tCLCH-10
tCLCH-10
Data Valid Delay
tCLDV
10
60
ns
—60
10
110
Data Hold Time
tCHDX
10
ns
——
10
Data Hold Time after WR
tWHDX
tCLCH-25
ns
tCLCH-30
tCLCH-30
Control Active Delay 1
tCVCTV
10
55
ns
10
70
10
110
Control Active Delay 2
tCHCTV
10
50
ns
10
60
10
110
Control Inactive Delay
tCVCTX
10
55
ns
10
70
10
110
Address Float to RD Active
tAZRL
0—
ns
0—
0
RD Active Delay
tCLRL
10
70
ns
10
100
10
165
Notes: 1. Signals at MSM82C84A-2 shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next
CLK.
3. Applies only to T2 state. (8 ns into T3)
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