參數(shù)資料
型號(hào)： MSP430F1101IPWR
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 8 MHz, RISC MICROCONTROLLER, PDSO20
封裝： PLASTIC, TSSOP-20
文件頁數(shù)： 9/43頁
文件大小： 869K
代理商： MSP430F1101IPWR
MSP430C11x1, MSP430F11x1A
MIXED SIGNAL MICROCONTROLLER
SLAS241I SEPTEMBER 1999 REVISED DECEMBER 2008
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs Ports P1 (P1.0 to P1.7) and P2 (P2.0 to P2.5)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
I(OHmax) = 1.5 mA
V
22V
See Note 1
VCC0.25
VCC
V
High-level output voltage
Port 1 and Port 2 (C11x1)
I(OHmax) = 6 mA
VCC = 2.2 V
See Note 2
VCC0.6
VCC
V
VOH
Port 1 and Port 2 (C11x1)
Port 1 (F11x1A)
I(OHmax) = 1.5 mA
V
3V
See Note 1
VCC0.25
VCC
V
Port 1 (F11x1A)
I(OHmax) = 6 mA
VCC = 3 V
See Note 2
VCC0.6
VCC
I(OHmax) = 1 mA
V
22V
See Note 3
VCC0.25
VCC
V
High-level output voltage
I(OHmax) = 3.4 mA
VCC = 2.2 V
See Note 3
VCC0.6
VCC
V
VOH
High level output voltage
Port 2 (F11x1A)
I(OHmax) = 1 mA
V
3V
See Note 3
VCC0.25
VCC
V
I(OHmax) = 3.4 mA
VCC = 3 V
See Note 3
VCC0.6
VCC
I(OLmax) = 1.5 mA
V
22V
See Note 1
VSS
VSS+0.25
V
Low-level output voltage
Port 1 and Port 2 (C11x1
I(OLmax) = 6 mA
VCC = 2.2 V
See Note 2
VSS
VSS+0.6
V
VOL
Port 1 and Port 2 (C11x1,
F11x1A)
I(OLmax) = 1.5 mA
V
=3V
See Note 1
VSS
VSS+0.25
V
F11x1A)
I(OLmax) = 6 mA
VCC = 3 V
See Note 2
VSS
VSS+0.6
NOTES:
1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum voltage
drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum voltage
drop specified.
3. One output loaded at a time.
output frequency
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fP20
P2.0/ACLK, CL = 20 pF
2.2 V/3 V
fSystem
fTAx
Output frequency
TA0, TA1, TA2, CL = 20 pF
Internal clock source, SMCLK signal applied (see Note 1)
2.2 V/3 V
dc
fSystem
MHz
fSMCLK = fLFXT1 = fXT1
40%
60%
P1 4/SMCLK
fSMCLK = fLFXT1 = fLF
2 2 V/3 V
35%
65%
P1.4/SMCLK,
CL = 20 pF
fSMCLK = fLFXT1/n
2.2 V/3 V
50%
15 ns
50%
50%+
15 ns
tXdc
Duty cycle of O/P
frequency
fSMCLK = fDCOCLK
2.2 V/3 V
50%
15 ns
50%
50%+
15 ns
frequency
P2 0/ACLK
fP20 = fLFXT1 = fXT1
40%
60%
P2.0/ACLK,
CL =20pF
fP20 = fLFXT1 = fLF
2.2 V/3 V
30%
70%
CL = 20 pF
fP20 = fLFXT1/n
50%
tTAdc
TA0, TA1, TA2, CL = 20 pF, duty cycle = 50%
2.2 V/3 V
0
±50
ns
NOTE 1: The limits of the system clock MCLK has to be met. MCLK and SMCLK can have different frequencies.
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