參數(shù)資料
型號(hào): MSP430F2619SKGD1
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, 16 MHz, RISC MICROCONTROLLER, UUC82
封裝: DIE-82
文件頁數(shù): 5/90頁
文件大?。?/td> 1141K
代理商: MSP430F2619SKGD1
SLAS697A
– MARCH 2010 – REVISED FEBRUARY 2011
Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range of 0FFFF
–0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector (located at address 0FFFEh) contains 0FFFFh (e.g., flash is not programmed), the CPU goes
into LPM4 immediately after power up.
SYSTEM
INTERRUPT SOURCE
INTERRUPT FLAG
WORD ADDRESS
PRIORITY
INTERRUPT
Power up
PORIFG
External reset
RSTIFG
Watchdog
WDTIFG
Reset
0x0FFFE
31, highest
Flash key violation
KEYV
PC out-of-range(1)
(2)
NMI
NMIIFG
(non)-maskable,
Oscillator fault
OFIFG
(non)-maskable,
0x0FFFC
30
Flash memory access violation
ACCVIFG (2) (3)
(non)-maskable
Timer_B7
TBCCR0 CCIFG(4)
maskable
0x0FFFA
29
TBCCR1 and TBCCR2
Timer_B7
maskable
0x0FFF8
28
CCIFGs, TBIFG(2) (4)
Comparator_A+
CAIFG
maskable
0x0FFF6
27
Watchdog timer+
WDTIFG
maskable
0x0FFF4
26
Timer_A3
TACCR0 CCIFG(4)
maskable
0x0FFF2
25
TACCR1 CCIFG,
Timer_A3
TACCR2 CCIFG,
maskable
0x0FFF0
24
TAIFG (2) (4)
USCI_A0/USCI_B0 receive
UCA0RXIFG, UCB0RXIFG(2) (5)
maskable
0x0FFEE
23
USCI_B0 I2C status
USCI_A0/USCI_B0 transmit
UCA0TXIFG, UCB0TXIFG(2)(6)
maskable
0x0FFEC
22
USCI_B0 I2C receive/transmit
ADC12
ADC12IFG(4)
maskable
0x0FFEA
21
0x0FFE8
20
I/O port P2 (eight flags)
P2IFG.0 to P2IFG.7(2) (4)
maskable
0x0FFE6
19
I/O port P1 (eight flags)
P1IFG.0 to P1IFG.7(2) (4)
maskable
0x0FFE4
18
USCI_A0/USCI_B1 receive
UCA1RXIFG, UCB1RXIFG(2) (5)
maskable
0x0FFE2
17
USCI_B1 I2C status
USCI_A1/USCI_B1 transmit
UCA1TXIFG, UCB1TXIFG(2) (6)
maskable
0x0FFE0
16
USCI_B1 I2C receive/transmit
DMA0IFG, DMA1IFG,
DMA
maskable
0x0FFDE
15
DMA2IFG(2) (4)
DAC12_0IFG, DAC12_1IFG(2)
DAC12
maskable
0x0FFDC
14
(4)
Reserved(7)(8)
Reserved
0x0FFDA to 0x0FFC0
13 to 0, lowest
(1)
A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0x00000
– 0x001FF)
or from within unused address range.
(2)
Multiple source flags
(3)
(non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.
(4)
Interrupt flags are located in the module.
(5)
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
(6)
In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
(7)
The address 0x0FFBE is used as bootstrap loader security key (BSLSKEY). A 0x0AA55 at this location disables the BSL completely. A
zero disables the erasure of the flash if an invalid password is supplied.
(8)
The interrupt vectors at addresses 0x0FFDC to 0x0FFC0 are not used in this device and can be used for regular program code if
necessary.
2010–2011, Texas Instruments Incorporated
13
Product Folder Link(s): MSP430F2619S-HT
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