參數(shù)資料
型號(hào)： MSP430F5326IRGCR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PQCC64
封裝： PLASTIC, VQFN-64
文件頁(yè)數(shù)： 12/68頁(yè)
文件大?。?/td> 793K
代理商： MSP430F5326IRGCR
PRODUCTPREVIEW
MSP430F532x
SLAS678 – AUGUST 2010
www.ti.com
DESCRIPTION
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with extensive
low-power modes is optimized to achieve extended battery life in portable measurement applications. The device
features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 5 s.
The MSP430F5329, MSP430F5327, and MSP430F5325 are microcontroller configurations with an integrated
3.3-V LDO, four 16-bit timers, a high-performance 12-bit analog-to-digital converter (ADC), two universal serial
communication interfaces (USCI), hardware multiplier, DMA, real-time clock module with alarm capabilities, and
63 I/O pins. The MSP430F5328, MSP430F5326, and MSP430F5324 include all of these peripherals but have 47
I/O pins.
Typical applications include analog and digital sensor systems, data loggers, etc., and various general-purpose
applications.
Family members available are summarized in Table 1.
Table 1. Family Members
USCI
Flash
SRAM
ADC12_A
Comp_B
Package
Channel A:
Channel B:
Device
Timer_A(1)
Timer_B(2)
I/O
(KB)
(Ch)
Type
UART/IrDA/
SPI/I2C
SPI
MSP430F5329
128
10
5, 3, 3
7
2
14 ext / 2 int
12
63
80 PN
64 RGC,
MSP430F5328
128
10
5, 3, 3
7
2
10 ext / 2 int
8
47
80 ZQE
MSP430F5327
96
8
5, 3, 3
7
2
14 ext / 2 int
12
63
80 PN
64 RGC,
MSP430F5326
96
8
5, 3, 3
7
2
10 ext / 2 int
8
47
80 ZQE
MSP430F5325
64
6
5, 3, 3
7
2
14 ext / 2 int
12
63
80 PN
64 RGC,
MSP430F5324
64
6
5, 3, 3
7
2
10 ext / 2 int
8
47
80 ZQE
(1)
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(2)
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
Ordering Information(1)
PACKAGED DEVICES(2)
TA
PLASTIC 80-PIN LQFP (PN)
PLASTIC 64-PIN QFN (RGC)
PLASTIC 80-BALL BGA (ZQE)
MSP430F5329IPN(3)
MSP430F5328IRGC(3)
MSP430F5328IZQE(3)
–40°C to 85°C
MSP430F5327IPN(3)
MSP430F5326IRGC(3)
MSP430F5326IZQE(3)
MSP430F5325IPN(3)
MSP430F5324IRGC(3)
MSP430F5324IZQE(3)
(1)
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2)
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
(3)
Product Preview
2
Copyright 2010, Texas Instruments Incorporated
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