參數(shù)資料
型號(hào)： MSP430F5326IRGCR
廠商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PQCC64
封裝： PLASTIC, VQFN-64
文件頁(yè)數(shù)： 2/68頁(yè)
文件大?。?/td> 793K
代理商： MSP430F5326IRGCR
PRODUCTPREVIEW
MSP430F532x
SLAS678 – AUGUST 2010
www.ti.com
Table 2. TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
I/O(1)
DESCRIPTION
NAME
PN
RGC
ZQE
General-purpose digital I/O (not available on 'F5328, 'F5326, 'F5324 devices)
Switch all PWM outputs high impedance input – TB0 (not available on 'F5328,
P3.7/TB0OUTH/SVMOUT
44
N/A
I/O
'F5326, 'F5324 devices)
SVM output (not available on 'F5328, 'F5326, 'F5324 devices)
General-purpose digital I/O with reconfigurable port mapping secondary
function
P4.0/PM_UCB1STE/
45
41
E8
I/O
Default mapping: Slave transmit enable – USCI_B1 SPI mode
PM_UCA1CLK
Default mapping: Clock signal input – USCI_A1 SPI slave mode
Default mapping: Clock signal output – USCI_A1 SPI master mode
General-purpose digital I/O with reconfigurable port mapping secondary
P4.1/PM_UCB1SIMO/
function
46
42
E7
I/O
PM_UCB1SDA
Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode
General-purpose digital I/O with reconfigurable port mapping secondary
P4.2/PM_UCB1SOMI/
function
47
43
D9
I/O
PM_UCB1SCL
Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock – USCI_B1 I2C mode
General-purpose digital I/O with reconfigurable port mapping secondary
function
P4.3/PM_UCB1CLK/
48
44
D8
I/O
Default mapping: Clock signal input – USCI_B1 SPI slave mode
PM_UCA1STE
Default mapping: Clock signal output – USCI_B1 SPI master mode
Default mapping: Slave transmit enable – USCI_A1 SPI mode
DVSS2
49
39
F9
Digital ground supply
DVCC2
50
40
E9
Digital power supply
General-purpose digital I/O with reconfigurable port mapping secondary
P4.4/PM_UCA1TXD/
function
51
45
D7
I/O
PM_UCA1SIMO
Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary
P4.5/PM_UCA1RXD/
function
52
46
C9
I/O
PM_UCA1SOMI
Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
General-purpose digital I/O with reconfigurable port mapping secondary
P4.6/PM_NONE
53
47
C8
I/O
function
Default mapping: no secondary function.
General-purpose digital I/O with reconfigurable port mapping secondary
P4.7/PM_NONE
54
48
C7
I/O
function
Default mapping: no secondary function.
General-purpose digital I/O (not available on 'F5328, 'F5326, 'F5324 devices)
P5.6/TB0.0
55
N/A
I/O
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on
'F5328, 'F5326, 'F5324 devices)
General-purpose digital I/O (not available on 'F5328, 'F5326, 'F5324 devices)
P5.7/TB0.1
56
N/A
I/O
TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on
'F5328, 'F5326, 'F5324 devices)
General-purpose digital I/O (not available on 'F5328, 'F5326, 'F5324 devices)
P7.4/TB0.2
57
N/A
I/O
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on
'F5328, 'F5326, 'F5324 devices)
General-purpose digital I/O (not available on 'F5328, 'F5326, 'F5324 devices)
P7.5/TB0.3
58
N/A
I/O
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on
'F5328, 'F5326, 'F5324 devices)
General-purpose digital I/O (not available on 'F5328, 'F5326, 'F5324 devices)
P7.6/TB0.4
59
N/A
I/O
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on
'F5328, 'F5326, 'F5324 devices)
General-purpose digital I/O (not available on 'F5328, 'F5326, 'F5324 devices)
TB0 clock signal TBCLK input (not available on 'F5328, 'F5326, 'F5324
P7.7/TB0CLK/MCLK
60
N/A
I/O
devices)
MCLK output (not available on 'F5328, 'F5326, 'F5324 devices)
10
Copyright 2010, Texas Instruments Incorporated
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