參數(shù)資料
型號(hào): MSP430F5326IRGCR
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, PQCC64
封裝: PLASTIC, VQFN-64
文件頁(yè)數(shù): 9/68頁(yè)
文件大小: 793K
代理商: MSP430F5326IRGCR
PRODUCTPREVIEW
MSP430F532x
www.ti.com
SLAS678 – AUGUST 2010
Flash Memory
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
Segments 0 to n may be erased in one step, or each segment may be individually erased.
Segments A to D can be erased individually. Segments A to D are also called information memory.
Segment A can be locked separately.
RAM Memory
The RAM memory is made up of n sectors. Each sector can be completely powered down to save leakage,
however all data is lost. Features of the RAM memory include:
RAM memory has n sectors. The size of a sector can be found in the Memory Organization section.
Each sector 0 to n can be complete disabled, however data retention is lost.
Each sector 0 to n automatically enters low power retention mode when possible.
Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x5xx Family User's Guide, literature number
Digital I/O
There are up to eight 8-bit I/O ports implemented: For 80-pin options, P1, P2, P3, P4, P5, P6, and P7 are
complete, and P8 is reduced to 3-bit I/O. For 64-pin options, P3 and P5 are reduced to 5-bit I/O and 6-bit I/O,
respectively, and P7 and P8 are completely removed. Port PJ contains four individual I/O ports, common to all
devices.
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Pullup or pulldown on all ports is programmable.
Drive strength on all ports is programmable.
Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Ports can be accessed byte-wise (P1 through P8) or word-wise in pairs (PA through PD).
Copyright 2010, Texas Instruments Incorporated
17
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