參數(shù)資料
型號(hào): MT29C2G24MAKLACG-75IT
元件分類: 存儲(chǔ)器
英文描述: SPECIALTY MEMORY CIRCUIT, PBGA152
封裝: GREEN, VFBGA-152
文件頁數(shù): 13/15頁
文件大?。?/td> 421K
代理商: MT29C2G24MAKLACG-75IT
PDF: 09005aef8326e5ac / Source: 09005aef8326e59a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
152ball_ nand_lpdram_j4xx_omap.fm - Rev. E 4/09 EN
7
2008 Micron Technology, Inc. All rights reserved.
152-Ball NAND Flash and Mobile LPDRAM PoP (TI OMAP) MCP
Ball Assignments and Descriptions
Preliminary
Notes: 1. Balls marked RFU may or may not be connected internally. These balls should not be used.
Contact the factory for details.
Table 2:
x8/x16 NAND Ball Descriptions
Symbol
Type
Description
ALE
Input
Address latch enable: When ALE is HIGH, addresses can be transferred to the on-chip address
register.
CE1#, CE0#
Input
Chip enable: Gates transfers between the host system and the NAND Flash device.
CLE
Input
Command latch enable: When CLE is HIGH, commands can be transferred to the on-chip
command register.
LOCK
Input
When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK
LOCK, connect LOCK to VSS during power-up, or leave it unconnected (internal pull-down).
RE#
Input
Read enable: Gates information from the NAND device to the host system.
WE#
Input
Write enable: Gates information from the host system to the NAND device.
WP#
Input
Write protect: Driving WP# LOW blocks ERASE and PROGRAM operations.
I/O[7:0]
(x8)
I/O[15:0]
(x16)
Input/
output
Data inputs/outputs: The bidirectional I/Os transfer address, data, and instruction information.
Data is output only during READ operations; at other times the I/Os are inputs.
I/O[15:8] are RFU1 for NAND x8 devices.
R/B#
Output
Ready/busy: Open-drain, active-LOW output that indicates when an internal operation is in
progress.
VCC
Supply
VCC: NAND power supply.
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