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參數(shù)資料
| 型號： | MT48LC16M4A2 |
| 廠商： | Micron Technology, Inc. |
| 元件分類： | DC/DC變換器 |
| 英文描述： | RSD Series - Econoline Unregulated DC-DC Converters; Input Voltage (Vdc): 24V; Output Voltage (Vdc): 3.3V; Power: 1W; 1kVDC and 3kVDC Isolation Options; Approved for Medical Applications; Suitable for Automated Assembly; 8, 10 and 12 pin Pinning Style Options; Optional Continuous Short Circuit Protected; Efficiency to 85% |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 15/55頁 |
| 文件大?。?/td> | 1458K |
| 代理商： | MT48LC16M4A2 |
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15
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2003, Micron Technology, Inc.
64Mb: x4, x8, x16
SDRAM
Upon completion of a burst, assuming no other com-
mands have been initiated, the DQs will go High-Z. A
full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a READ command. In either case, a continu-
ous flow of data can be maintained. The first data ele-
ment from the new burst follows either the last ele-
ment of a completed burst or the last desired data ele-
ment of a longer burst which is being truncated.
The new READ command should be issued
x
cycles
REA Ds
READ bursts are initiated with a READ command,
as shown in Figure 5.
The starting column and bank addresses are pro-
vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric READ commands used in the following illustra-
tions, auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available fol-
lowing the CAS latency after the READ command. Each
subsequent data-out element will be valid by the next
positive clock edge. Figure 6 shows general timing for
each possible CAS latency setting.
Figure 5
READ Command
Figure 6
CAS Latency
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
t
D
OUT
tOH
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON’T CARE
UNDEFINED
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
t
D
OUT
tOH
COMMAND
NOP
READ
tAC
NOP
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A0-A9: x4
A0-A8: x8
A0-A7: x16
A10
BA0,1
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
BANK
ADDRESS
A11: x4
A9, A11: x8
A8, A9, A11: x16
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT48LC16M4A2TG | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM |
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