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參數(shù)資料
| 型號： | MT48LC4M32TG-10 |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 3/69頁 |
| 文件大小： | 6213K |
| 代理商： | MT48LC4M32TG-10 |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
11
2001 Micron Technology, Inc. All rights reserved.
Table 5:
Pin Descriptions: 54-Pin TSOP (x16 Only)
TSOP PIN NUMBER
SYMBOL
TYPE
DESCRIPTION
38
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
37
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.
19
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
16, 17, 18
WE#, CAS#,
RAS#
Input
Command Inputs: WE#, CAS#, and RAS# (along with CS#) define the
command being entered.
15, 39
DQML,
DQMH
Input
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when during a READ cycle. DQM0 corresponds to
DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to
DQ16–DQ23 and DQM3 corresponds to DQ24–DQ31. LDQM corresponds
to DQ0–DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are
considered same state when referenced as DQM.
20, 21
BA0, BA1
Input
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied. These pins also
provide the op-code during a LOAD MODE REGISTER command
23, 24, 25, 29, 30,
31, 32, 33, 34, 22, 35
A0–A5
A6-A11
Input
Address Inputs: A0–A11 are sampled during the ACTIVE command (row-
address A0–A11) and READ/WRITE command (column-address A0–A7;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
2, 4, 5, 7, 8, 10, 11, 13,
42, 49,45, 47, 48, 50, 51
DQ0–DQ7
DQ8-DQ15
I/O
Data Input/Output: Data bus (x16 Only)
36, 40
NC
–
No Connect: These pins should be left unconnected. Pin 36 is a no connect
for this part but may be used as A12 in future designs.
3, 9, 43, 49
VDDQ
Supply DQ Power: Isolated DQ power on the die to improve noise immunity.
6, 12, 46, 52
VSSQ
Supply DQ Ground: Isolated DQ power on the die to improve noise immunity.
1, 14, 27
VDD
Supply Power Supply: Voltage dependant on option.
28, 41, 54
VSS
Supply Ground.
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