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參數(shù)資料
| 型號： | MT48LC4M32TG-10 |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 5/69頁 |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48LC4M32TG-10 |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
13
2001 Micron Technology, Inc. All rights reserved.
length is set to two; by A2-A8 (x16) or A2-A7 (x32) when
the burst length is set to four; and by A3-A8 (x16) or A3-
A7 (x32) when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. Full-
page bursts wrap within the page if the boundary is
reached.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3. Note only a
sequential burst is allowed for full page bursts.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6 on page 14.
Figure 7: Mode Register Definition
10
M3 = 0
1
2
4
8
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Valid
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
1
2
3
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7 A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
65
4
3
8
2
1
0
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Op Mode
A10
Reserved WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
BA0
BA1
M9
M7 M6 M5 M4
M3
M8
M2 M1 M0
M10
11
A11
M11
M12
M13
MR
13
12
Mode Register Definition
Program Mode Register
Program Extended Mode Register
0
1
0
M13
M12
Valid
-
M9
0
-
M10
0
-
M11
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