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參數(shù)資料
| 型號： | MT48LC4M32TG-10 |
| 元件分類： | DRAM |
| 英文描述： | 4M X 32 SYNCHRONOUS DRAM, 7 ns, PDSO54 |
| 封裝： | 0.400 INCH, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 7/69頁 |
| 文件大?。?/td> | 6213K |
| 代理商： | MT48LC4M32TG-10 |
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128Mb: x16, x32
MOBILE SDRAM
09005aef8071a76b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx16x32Mobile_2.fm - Rev. G (DRAFT) 7/04 EN
15
2001 Micron Technology, Inc. All rights reserved.
Write Burst Mode
When M9=0, the burst length programmed into M0-
M2 applies to both READ and WRITE burst. If M9 = 1,
all WRITE bursts will only be single location access
regardless of the burst length setting in the mode regis-
ter. READ burst lengths are unaffected by the state of
M9.
Operating Mode
The normal operating mode is selected by setting
M7, M8, M10 and M11 to zero; all the other combina-
tions of values for M7, M8, M10 and M11 are reserved
for future use and/or test modes.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Extended Mode Register
The Extended Mode Register controls the functions
beyond those controlled by the Mode Register. These
additional functions are special features of the Mobile
device. They include Temperature Compensated Self
Refresh Control (TCSR), and Partial Array Self Refresh
(PASR).
Figure 9: Extended Mode Register
The Extended Mode Register is programmed via the
Mode Register Set command (BA1=1,BA0=0) and
retains the stored information until it is programmed
again or the device loses power.
The Extended Mode Register must be programmed
with E5 through E11 set to “0”. The Extended Mode
Register must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specified time before initiating any subsequent opera-
tion. Violating either of these requirements results in
unspecified operation. The Extended Mode Register
must be programmed in order to ensure proper opera-
tion.
Temperature Compensated Self Refresh
Temperature Compensated Self Refresh (TCSR)
allows the controller to program the Refresh interval
during SELF REFRESH mode, according to the case
temperature of the Mobile device. This allows great
power savings during SELF REFRESH during most
operating temperature ranges. Only during extreme
Table 7:
CAS Latency
SPEED
ALLOWABLE OPERATING FREQUENCY
(MHZ)
CAS
LATENCY = 1
CAS
LATENCY = 2
CAS
LATENCY = 3
-75M
-
≤ 100
≤ 133
- 8
≤ 50
≤ 100
≤ 125
- 10
≤ 40
≤ 83
≤ 100
Address Bus
97
6
5
4
3
82
1
PASR
TCSR
set to "0"
EMR
E13 E12
A11
E11
A10
E10
A9
E9
A8
E8
A7
E7
A6
E6
A5
E5
A4
E4
A3
E3
A2
E2
A1
E1
A0
E0
10
11
12
13
Notes: 1. M13 and M12 (BA1 and BA0) must be “1, 0” to select the Extended Mode Register
(vs. the base Mode Register).
2. RFU: Reserved for Future Use
Partial Array Self Refresh Coverage
FullArray (All Banks)
Half Array (BA1 = 0)
Quarter Array (BA1 = BA0 = 0)
RFU
BA1 BA0
0
1
Mode Register Definintion
Mode Register
Reserved
Extended Mode Register
Resereved
M13
0
1
0
1
M12
0
E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 Operating Mode
0
-
0
-
0
-
0
-
0
-
Va l i d
-
Normal Operation
All other states reserved
Extended Mode
Register (Ex)
0
-
0
-
E2
0
1
E1
0
1
0
1
E0
0
1
0
1
0
1
0
1
Maximum Case Temp
85C
70C
45C
15C
E4
1
0
1
E3
1
0
1
0
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